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Re: [RFC] Use .opt for the SPARC port
> So your main objection to my patch is that the string "Mask(...)"
> doesn't feature in the mask definition? If so, I suppose we could
> just allow stand-alone "Mask(FOO)" records. Would that be a reasonable
> compromise?
Third revision attached.
2005-04-11 ?Eric Botcazou ?<ebotcazou@libertysurf.fr>
* optc-gen.awk: Handle stand-alone Mask records.
* opth-gen.awk: Likewise.
* doc/options.texi (Option file format): Document them.
* config.gcc (sparc-*-netbsdelf*, sparc-*-linux*, sparc64-*-freebsd*,
sparc64-*-linux*, sparc64-*-netbsd*): Add sparc/long-double-switch.opt.
(sparc64-*-openbsd*, sparc64-*-elf*): Add sparc/little-endian.opt.
* config/sparc/sparc.h (MASK_FPU, MASK_UNALIGNED_DOUBLES,
MASK_V8, MASK_SPARCLITE, MASK_SPARCLET, MASK_V9,
MASK_DEPRECATED_V8_INSNS, MASK_IMPURE_TEXT, MASK_APP_REGS,
MASK_HARD_QUAD, MASK_LITTLE_ENDIAN, MASK_PTR64, MASK_64BIT,
MASK_STACK_BIAS, MASK_FPU_SET, MASK_VIS, MASK_V8PLUS,
MASK_FASTER_STRUCTS, MASK_LONG_DOUBLE_128): Delete.
(TARGET_FPU, TARGET_UNALIGNED_DOUBLES, TARGET_V8, TARGET_SPARCLITE,
TARGET_SPARCLET, TARGET_V9, TARGET_DEPRECATED_V8_INSNS,
TARGET_IMPURE_TEXT, TARGET_APP_REGS, MASK_HARD_QUAD, TARGET_LITTLE_ENDIAN,
TARGET_PTR64, TARGET_64BIT, MASK_STACK_BIAS, TARGET_FPU_SET, TARGET_VIS,
TARGET_V8PLUS, TARGET_FASTER_STRUCTS, TARGET_LONG_DOUBLE_128): Likewise.
(TARGET_SWITCHES, SUBTARGET_SWITCHES): Likewise.
(TARGET_OPTIONS, SUBTARGET_OPTIONS): Likewise.
* config/sparc/freebsd.h (SUBTARGET_SWITCHES): Likewise.
* config/sparc/linux.h (SUBTARGET_SWITCHES): Likewise.
* config/sparc/linux64.h (SUBTARGET_SWITCHES): Likewise.
* config/sparc/netbsd-elf.h (SUBTARGET_SWITCHES): Likewise.
* config/sparc/sp64-elf.h (SUBTARGET_SWITCHES): Likewise.
* config/sparc/sparc.c (fpu_option_set): New global.
(sparc_handle_option): New function.
(sparc_override_options): Test fpu_option_set instead of TARGET_FPU_SET.
(TARGET_DEFAULT_TARGET_FLAGS): Set to TARGET_DEFAULT.
(TARGET_HANDLE_OPTION): Set to sparc_handle_option.
* config/sparc/sparc.opt: New file.
* config/sparc/little-endian.opt: Likewise.
* config/sparc/long-double-switch.opt: Likewise.
--
Eric Botcazou
Index: config.gcc
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config.gcc,v
retrieving revision 1.529
diff -u -r1.529 config.gcc
--- config.gcc 4 Apr 2005 17:18:49 -0000 1.529
+++ config.gcc 11 Apr 2005 11:19:36 -0000
@@ -1910,6 +1910,7 @@
;;
sparc-*-netbsdelf*)
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h"
+ extra_options="${extra_options} sparc/long-double-switch.opt"
;;
sparc-*-openbsd*)
tm_defines=OBSD_OLD_GAS
@@ -1921,6 +1922,7 @@
;;
sparc64-*-openbsd*)
tm_file="sparc/openbsd1-64.h ${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sp64-elf.h openbsd.h sparc/openbsd64.h"
+ extra_options="${extra_options} sparc/little-endian.opt"
gas=yes gnu_ld=yes
with_cpu=ultrasparc
;;
@@ -1932,6 +1934,7 @@
;;
sparc-*-linux*) # SPARC's running GNU/Linux, libc6
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux.h"
+ extra_options="${extra_options} sparc/long-double-switch.opt"
tmake_file="${tmake_file} sparc/t-crtfm"
;;
sparc-*-rtems*)
@@ -2030,12 +2033,14 @@
;;
sparc64-*-elf*)
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/sp64-elf.h"
+ extra_options="${extra_options} sparc/little-endian.opt"
tmake_file="${tmake_file} sparc/t-crtfm"
extra_parts="crtbegin.o crtend.o"
use_fixproto=yes
;;
sparc64-*-freebsd*|ultrasparc-*-freebsd*)
tm_file="${tm_file} ${fbsd_tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/freebsd.h"
+ extra_options="${extra_options} sparc/long-double-switch.opt"
tmake_file="${tmake_file} sparc/t-crtfm"
case "x$with_cpu" in
xultrasparc) ;;
@@ -2045,13 +2050,15 @@
need_64bit_hwint=yes
;;
sparc64-*-linux*) # 64-bit SPARC's running GNU/Linux
- tmake_file="${tmake_file} sparc/t-linux64 sparc/t-crtfm"
tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux64.h"
+ extra_options="${extra_options} sparc/long-double-switch.opt"
+ tmake_file="${tmake_file} sparc/t-linux64 sparc/t-crtfm"
;;
sparc64-*-netbsd*)
- tmake_file="${tmake_file} sparc/t-netbsd64"
tm_file="sparc/biarch64.h ${tm_file}"
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h"
+ extra_options="${extra_options} sparc/long-double-switch.opt"
+ tmake_file="${tmake_file} sparc/t-netbsd64"
;;
strongarm-*-elf*)
tm_file="arm/strongarm-elf.h dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/aout.h arm/arm.h"
Index: optc-gen.awk
===================================================================
RCS file: /cvs/gcc/gcc/gcc/optc-gen.awk,v
retrieving revision 2.2
diff -u -r2.2 optc-gen.awk
--- optc-gen.awk 30 Mar 2005 06:24:35 -0000 2.2
+++ optc-gen.awk 11 Apr 2005 11:19:36 -0000
@@ -42,10 +42,13 @@
n_langs++;
}
else {
- opts[n_opts] = $1
- flags[n_opts] = $2
- help[n_opts] = $3
- n_opts++;
+ name = opt_args("Mask", $1)
+ if (name == "") {
+ opts[n_opts] = $1
+ flags[n_opts] = $2
+ help[n_opts] = $3
+ n_opts++;
+ }
}
}
Index: opth-gen.awk
===================================================================
RCS file: /cvs/gcc/gcc/gcc/opth-gen.awk,v
retrieving revision 2.4
diff -u -r2.4 opth-gen.awk
--- opth-gen.awk 30 Mar 2005 06:26:19 -0000 2.4
+++ opth-gen.awk 11 Apr 2005 11:19:36 -0000
@@ -26,7 +26,8 @@
BEGIN {
n_opts = 0
n_langs = 0
- quote = "\042"
+ n_extra_masks = 0
+ quote = "\042"
comma = ","
FS=SUBSEP
}
@@ -38,10 +39,16 @@
n_langs++;
}
else {
- opts[n_opts] = $1
- flags[n_opts] = $2
- help[n_opts] = $3
- n_opts++;
+ name = opt_args("Mask", $1)
+ if (name == "") {
+ opts[n_opts] = $1
+ flags[n_opts] = $2
+ help[n_opts] = $3
+ n_opts++;
+ }
+ else {
+ extra_masks[n_extra_masks++] = name
+ }
}
}
@@ -54,6 +61,7 @@
print "#define OPTIONS_H"
print ""
print "extern int target_flags;"
+print ""
for (i = 0; i < n_opts; i++) {
name = var_name(flags[i]);
@@ -73,6 +81,9 @@
if (name != "" && !flag_set_p("MaskExists", flags[i]))
print "#define MASK_" name " (1 << " masknum++ ")"
}
+for (i = 0; i < n_extra_masks; i++) {
+ print "#define MASK_" extra_masks[i] " (1 << " masknum++ ")"
+}
if (masknum > 31)
print "#error too many target masks"
print ""
@@ -83,6 +94,10 @@
print "#define TARGET_" name \
" ((target_flags & MASK_" name ") != 0)"
}
+for (i = 0; i < n_extra_masks; i++) {
+ print "#define TARGET_" extra_masks[i] \
+ " ((target_flags & MASK_" extra_masks[i] ") != 0)"
+}
print ""
for (i = 0; i < n_opts; i++) {
Index: config/sparc/freebsd.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/freebsd.h,v
retrieving revision 1.30
diff -u -r1.30 freebsd.h
--- config/sparc/freebsd.h 22 Jan 2005 12:53:25 -0000 1.30
+++ config/sparc/freebsd.h 11 Apr 2005 11:19:36 -0000
@@ -72,11 +72,6 @@
/* Definitions for 64-bit SPARC running systems with ELF. */
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- {"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
- {"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (FreeBSD/sparc64 ELF)");
Index: config/sparc/linux.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/linux.h,v
retrieving revision 1.69
diff -u -r1.69 linux.h
--- config/sparc/linux.h 4 Apr 2005 15:29:04 -0000 1.69
+++ config/sparc/linux.h 11 Apr 2005 11:19:36 -0000
@@ -86,11 +86,6 @@
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with ELF)");
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
-{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
Index: config/sparc/linux64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/linux64.h,v
retrieving revision 1.92
diff -u -r1.92 linux64.h
--- config/sparc/linux64.h 4 Apr 2005 15:29:04 -0000 1.92
+++ config/sparc/linux64.h 11 Apr 2005 11:19:37 -0000
@@ -106,11 +106,6 @@
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_MEDLOW
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
-{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
#undef WCHAR_TYPE
#define WCHAR_TYPE "int"
Index: config/sparc/netbsd-elf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/netbsd-elf.h,v
retrieving revision 1.27
diff -u -r1.27 netbsd-elf.h
--- config/sparc/netbsd-elf.h 22 Jan 2005 12:53:25 -0000 1.27
+++ config/sparc/netbsd-elf.h 11 Apr 2005 11:19:37 -0000
@@ -195,13 +195,6 @@
{ "netbsd_entry_point", NETBSD_ENTRY_POINT },
-/* What extra switches do we need? */
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- {"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
- {"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
-
-
/* Build a compiler that supports -m32 and -m64? */
#ifdef SPARC_BI_ARCH
Index: config/sparc/sp64-elf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sp64-elf.h,v
retrieving revision 1.36
diff -u -r1.36 sp64-elf.h
--- config/sparc/sp64-elf.h 24 Jan 2005 21:31:52 -0000 1.36
+++ config/sparc/sp64-elf.h 11 Apr 2005 11:19:37 -0000
@@ -81,12 +81,6 @@
|| (CHAR) == 'h' \
|| (CHAR) == 'z')
-/* V9 chips can handle either endianness. */
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN, N_("Generate code for big endian") }, \
-{"little-endian", MASK_LITTLE_ENDIAN, N_("Generate code for little endian") },
-
#undef BYTES_BIG_ENDIAN
#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
Index: config/sparc/sparc.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.c,v
retrieving revision 1.361
diff -u -r1.361 sparc.c
--- config/sparc/sparc.c 6 Apr 2005 11:53:53 -0000 1.361
+++ config/sparc/sparc.c 11 Apr 2005 11:19:40 -0000
@@ -299,6 +299,7 @@
/* 1 if the next opcode is to be specially indented. */
int sparc_indent_opcode = 0;
+static bool sparc_handle_option (size_t, const char *, int);
static void sparc_init_modes (void);
static void scan_record_type (tree, int *, int *, int *);
static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
@@ -372,6 +373,7 @@
/* Code model option as passed by user. */
const char *sparc_cmodel_string;
+
/* Parsed value. */
enum cmodel sparc_cmodel;
@@ -388,7 +390,10 @@
/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
enum processor_type sparc_cpu;
-
+
+/* Whether an FPU option was specified. */
+static bool fpu_option_set = false;
+
/* Initialize the GCC target structure. */
/* The sparc default is to use .half rather than .short for aligned
@@ -506,11 +511,45 @@
#undef TARGET_RELAXED_ORDERING
#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION sparc_handle_option
+
#undef TARGET_ASM_FILE_END
#define TARGET_ASM_FILE_END sparc_file_end
struct gcc_target targetm = TARGET_INITIALIZER;
-
+
+/* Implement TARGET_HANDLE_OPTION. */
+
+static bool
+sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+{
+ switch (code)
+ {
+ case OPT_mfpu:
+ case OPT_mhard_float:
+ case OPT_msoft_float:
+ fpu_option_set = true;
+ break;
+
+ case OPT_mcpu_:
+ sparc_select[1].string = arg;
+ break;
+
+ case OPT_mtune_:
+ sparc_select[2].string = arg;
+ break;
+
+ case OPT_mcmodel_:
+ sparc_cmodel_string = arg;
+ break;
+ }
+
+ return true;
+}
+
/* Validate and override various options, and do some machine dependent
initialization. */
@@ -658,13 +697,9 @@
}
/* If -mfpu or -mno-fpu was explicitly used, don't override with
- the processor default. Clear MASK_FPU_SET to avoid confusing
- the reverse mapping from switch values to names. */
- if (TARGET_FPU_SET)
- {
- target_flags = (target_flags & ~MASK_FPU) | fpu;
- target_flags &= ~MASK_FPU_SET;
- }
+ the processor default. */
+ if (fpu_option_set)
+ target_flags = (target_flags & ~MASK_FPU) | fpu;
/* Don't allow -mvis if FPU is disabled. */
if (! TARGET_FPU)
Index: config/sparc/sparc.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.h,v
retrieving revision 1.274
diff -u -r1.274 sparc.h
--- config/sparc/sparc.h 4 Apr 2005 15:29:10 -0000 1.274
+++ config/sparc/sparc.h 11 Apr 2005 11:19:42 -0000
@@ -483,122 +483,14 @@
/* Show we can debug even without a frame pointer. */
#define CAN_DEBUG_WITHOUT_FP
+/* Option handling. */
+
#define OVERRIDE_OPTIONS sparc_override_options ()
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
-/* Nonzero if we should generate code to use the fpu. */
-#define MASK_FPU 1
-#define TARGET_FPU (target_flags & MASK_FPU)
-
-/* Nonzero if we should assume that double pointers might be unaligned.
- This can happen when linking gcc compiled code with other compilers,
- because the ABI only guarantees 4 byte alignment. */
-#define MASK_UNALIGNED_DOUBLES 4
-#define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
-
-/* Nonzero means that we should generate code for a v8 sparc. */
-#define MASK_V8 0x8
-#define TARGET_V8 (target_flags & MASK_V8)
-
-/* Nonzero means that we should generate code for a sparclite.
- This enables the sparclite specific instructions, but does not affect
- whether FPU instructions are emitted. */
-#define MASK_SPARCLITE 0x10
-#define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
-
-/* Nonzero if we're compiling for the sparclet. */
-#define MASK_SPARCLET 0x20
-#define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
-
-/* Nonzero if we're compiling for v9 sparc.
- Note that v9's can run in 32 bit mode so this doesn't necessarily mean
- the word size is 64. */
-#define MASK_V9 0x40
-#define TARGET_V9 (target_flags & MASK_V9)
-
-/* Nonzero to generate code that uses the instructions deprecated in
- the v9 architecture. This option only applies to v9 systems. */
-/* ??? This isn't user selectable yet. It's used to enable such insns
- on 32 bit v9 systems and for the moment they're permanently disabled
- on 64 bit v9 systems. */
-#define MASK_DEPRECATED_V8_INSNS 0x80
-#define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
-
/* Mask of all CPU selection flags. */
#define MASK_ISA \
(MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
-/* Nonzero means don't pass `-assert pure-text' to the linker. */
-#define MASK_IMPURE_TEXT 0x100
-#define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
-
-/* 0x200 is unused */
-
-/* Nonzero means use the registers that the SPARC ABI reserves for
- application software. This must be the default to coincide with the
- setting in FIXED_REGISTERS. */
-#define MASK_APP_REGS 0x400
-#define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
-
-/* Option to select how quad word floating point is implemented.
- When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
- Otherwise, we use the SPARC ABI quad library functions. */
-#define MASK_HARD_QUAD 0x800
-#define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
-
-/* Nonzero on little-endian machines. */
-/* ??? Little endian support currently only exists for sparc86x-elf and
- sparc64-elf configurations. May eventually want to expand the support
- to all targets, but for now it's kept local to only those two. */
-#define MASK_LITTLE_ENDIAN 0x1000
-#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
-
-/* 0x2000, 0x4000 are unused */
-
-/* Nonzero if pointers are 64 bits. */
-#define MASK_PTR64 0x8000
-#define TARGET_PTR64 (target_flags & MASK_PTR64)
-
-/* Nonzero if generating code to run in a 64 bit environment.
- This is intended to only be used by TARGET_ARCH{32,64} as they are the
- mechanism used to control compile time or run time selection. */
-#define MASK_64BIT 0x10000
-#define TARGET_64BIT (target_flags & MASK_64BIT)
-
-/* 0x20000,0x40000 unused */
-
-/* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
- adding 2047 to %sp. This option is for v9 only and is the default. */
-#define MASK_STACK_BIAS 0x80000
-#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
-
-/* 0x100000,0x200000 unused */
-
-/* Nonzero means -m{,no-}fpu was passed on the command line. */
-#define MASK_FPU_SET 0x400000
-#define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
-
-/* Use the UltraSPARC Visual Instruction Set extensions. */
-#define MASK_VIS 0x1000000
-#define TARGET_VIS (target_flags & MASK_VIS)
-
-/* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
- the current out and global registers and Linux 2.2+ as well. */
-#define MASK_V8PLUS 0x2000000
-#define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
-
-/* Force a the fastest alignment on structures to take advantage of
- faster copies. */
-#define MASK_FASTER_STRUCTS 0x4000000
-#define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
-
-/* Use IEEE quad long double. */
-#define MASK_LONG_DOUBLE_128 0x8000000
-#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
-
/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
to get high 32 bits. False in V8+ or V9 because multiply stores
@@ -613,79 +505,11 @@
(TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
|| TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
-
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
- { {"fpu", MASK_FPU | MASK_FPU_SET, \
- N_("Use hardware fp") }, \
- {"no-fpu", -MASK_FPU, \
- N_("Do not use hardware fp") }, \
- {"no-fpu", MASK_FPU_SET, NULL, }, \
- {"hard-float", MASK_FPU | MASK_FPU_SET, \
- N_("Use hardware fp") }, \
- {"soft-float", -MASK_FPU, \
- N_("Do not use hardware fp") }, \
- {"soft-float", MASK_FPU_SET, NULL }, \
- {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
- N_("Assume possible double misalignment") }, \
- {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
- N_("Assume all doubles are aligned") }, \
- {"impure-text", MASK_IMPURE_TEXT, \
- N_("Pass -assert pure-text to linker") }, \
- {"no-impure-text", -MASK_IMPURE_TEXT, \
- N_("Do not pass -assert pure-text to linker") }, \
- {"app-regs", MASK_APP_REGS, \
- N_("Use ABI reserved registers") }, \
- {"no-app-regs", -MASK_APP_REGS, \
- N_("Do not use ABI reserved registers") }, \
- {"hard-quad-float", MASK_HARD_QUAD, \
- N_("Use hardware quad fp instructions") }, \
- {"soft-quad-float", -MASK_HARD_QUAD, \
- N_("Do not use hardware quad fp instructions") }, \
- {"v8plus", MASK_V8PLUS, \
- N_("Compile for v8plus ABI") }, \
- {"no-v8plus", -MASK_V8PLUS, \
- N_("Do not compile for v8plus ABI") }, \
- {"vis", MASK_VIS, \
- N_("Utilize Visual Instruction Set") }, \
- {"no-vis", -MASK_VIS, \
- N_("Do not utilize Visual Instruction Set") }, \
- {"ptr64", MASK_PTR64, \
- N_("Pointers are 64-bit") }, \
- {"ptr32", -MASK_PTR64, \
- N_("Pointers are 32-bit") }, \
- {"32", -MASK_64BIT, \
- N_("Use 32-bit ABI") }, \
- {"64", MASK_64BIT, \
- N_("Use 64-bit ABI") }, \
- {"stack-bias", MASK_STACK_BIAS, \
- N_("Use stack bias") }, \
- {"no-stack-bias", -MASK_STACK_BIAS, \
- N_("Do not use stack bias") }, \
- {"faster-structs", MASK_FASTER_STRUCTS, \
- N_("Use structs on stronger alignment for double-word copies") }, \
- {"no-faster-structs", -MASK_FASTER_STRUCTS, \
- N_("Do not use structs on stronger alignment for double-word copies") }, \
- {"relax", 0, \
- N_("Optimize tail call instructions in assembler and linker") }, \
- {"no-relax", 0, \
- N_("Do not optimize tail call instructions in assembler or linker") }, \
- SUBTARGET_SWITCHES \
- { "", TARGET_DEFAULT, ""}}
-
/* MASK_APP_REGS must always be the default because that's what
FIXED_REGISTERS is set to and -ffixed- is processed before
CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
-/* This is meant to be redefined in target specific files. */
-#define SUBTARGET_SWITCHES
-
/* Processor type.
These must match the values for the cpu attribute in sparc.md. */
enum processor_type {
@@ -712,20 +536,6 @@
Every file includes us, but not every file includes insn-attr.h. */
#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
-#define TARGET_OPTIONS \
-{ \
- { "cpu=", &sparc_select[1].string, \
- N_("Use features of and schedule code for given CPU"), 0}, \
- { "tune=", &sparc_select[2].string, \
- N_("Schedule code for given CPU"), 0}, \
- { "cmodel=", &sparc_cmodel_string, \
- N_("Use given SPARC code model"), 0}, \
- SUBTARGET_OPTIONS \
-}
-
-/* This is meant to be redefined in target specific files. */
-#define SUBTARGET_OPTIONS
-
/* Support for a compile-time default CPU, et cetera. The rules are:
--with-cpu is ignored if -mcpu is specified.
--with-tune is ignored if -mtune is specified.
Index: doc/options.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/options.texi,v
retrieving revision 1.2
diff -u -r1.2 options.texi
--- doc/options.texi 30 Mar 2005 06:26:20 -0000 1.2
+++ doc/options.texi 11 Apr 2005 11:19:42 -0000
@@ -25,15 +25,17 @@
the file and are preceded by semicolons. Whitespace is allowed before
the semicolon.
-The files can contain two types of record: language definitions and
-option definitions.
+The files can contain the following types of record:
-A language definition record has two fields: the string
-@samp{Language} and the name of the language. Once a language has
-been declared in this way, it can be used as an option property.
+@itemize @bullet
+@item
+A language definition record. ?These records have two fields: the
+string @samp{Language} and the name of the language. ?Once a language
+has been declared in this way, it can be used as an option property.
@xref{Option properties}.
-An option definition record has the following fields:
+@item
+An option definition record. ?These records have the following fields:
@enumerate
@item
@@ -59,6 +61,21 @@
tab forms the help text. This allows you to elaborate on what type
of argument the option takes.
+@item
+A target mask record. ?These records have one field of the form
+@samp{Mask(@var{x})}. ?The options-processing script will automatically
+allocate a bit in @code{target_flags} (@pxref{Run-time Target}) for
+each mask name @var{x} and set the macro @code{MASK_@var{x}} to the
+appropriate bitmask. ?It will also declare a @code{TARGET_@var{x}}
+macro that has the value 1 when bit @code{MASK_@var{x}} is set and
+0 otherwise.
+
+They are primarily intended to declare target masks that are not
+associated with user options, either because these masks represent
+internal switches or because the options are not available on all
+configurations and yet the masks always need to be defined.
+@end itemize
+
@node Option properties
@section Option properties
*** /dev/null 2004-10-02 05:17:35.000000000 +0200
--- config/sparc/sparc.opt 2005-04-11 12:47:01.952455680 +0200
***************
*** 0 ****
--- 1,123 ----
+ ; Options for the SPARC port of the compiler
+ ;
+ ; Copyright (C) 2005 Free Software Foundation, Inc.
+ ;
+ ; This file is part of GCC.
+ ;
+ ; GCC is free software; you can redistribute it and/or modify it under
+ ; the terms of the GNU General Public License as published by the Free
+ ; Software Foundation; either version 2, or (at your option) any later
+ ; version.
+ ;
+ ; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ; License for more details.
+ ;
+ ; You should have received a copy of the GNU General Public License
+ ; along with GCC; see the file COPYING. If not, write to the Free
+ ; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ ; 02111-1307, USA.
+
+ mfpu
+ Target Report Mask(FPU)
+ Use hardware FP
+
+ mhard-float
+ Target RejectNegative Mask(FPU) MaskExists
+ Use hardware FP
+
+ msoft-float
+ Target RejectNegative InverseMask(FPU)
+ Do not use hardware FP
+
+ munaligned-doubles
+ Target Report Mask(UNALIGNED_DOUBLES)
+ Assume possible double misalignment
+
+ mimpure-text
+ Target Report
+ Pass -assert pure-text to linker
+
+ mapp-regs
+ Target Report Mask(APP_REGS)
+ Use ABI reserved registers
+
+ mhard-quad-float
+ Target Report RejectNegative Mask(HARD_QUAD)
+ Use hardware quad FP instructions
+
+ msoft-quad-float
+ Target Report RejectNegative InverseMask(HARD_QUAD)
+ Do not use hardware quad fp instructions
+
+ mv8plus
+ Target Report Mask(V8PLUS)
+ Compile for V8+ ABI
+
+ mvis
+ Target Report Mask(VIS)
+ Use UltraSPARC Visual Instruction Set extensions
+
+ mptr64
+ Target Report RejectNegative Mask(PTR64)
+ Pointers are 64-bit
+
+ mptr32
+ Target Report RejectNegative InverseMask(PTR64)
+ Pointers are 32-bit
+
+ m64
+ Target Report RejectNegative Mask(64BIT)
+ Use 64-bit ABI
+
+ m32
+ Target Report RejectNegative InverseMask(64BIT)
+ Use 32-bit ABI
+
+ mstack-bias
+ Target Report Mask(STACK_BIAS)
+ Use stack bias
+
+ mfaster-structs
+ Target Report Mask(FASTER_STRUCTS)
+ Use structs on stronger alignment for double-word copies
+
+ mrelax
+ Target
+ Optimize tail call instructions in assembler and linker
+
+ mcpu=
+ Target RejectNegative Joined
+ Use features of and schedule code for given CPU
+
+ mtune=
+ Target RejectNegative Joined
+ Schedule code for given CPU
+
+ mcmodel=
+ Target RejectNegative Joined
+ Use given SPARC-V9 code model
+
+
+ Mask(LITTLE_ENDIAN)
+ ;; Generate code for little-endian
+
+ Mask(LONG_DOUBLE_128)
+ ;; Use 128-bit long double
+
+ Mask(SPARCLITE)
+ ;; Generate code for SPARClite
+
+ Mask(SPARCLET)
+ ;; Generate code for SPARClet
+
+ Mask(V8)
+ ;; Generate code for SPARC-V8
+
+ Mask(V9)
+ ;; Generate code for SPARC-V9
+
+ Mask(DEPRECATED_V8_INSNS)
+ ;; Generate code that uses the V8 instructions deprecated
+ ;; in the V9 architecture.
*** /dev/null 2004-10-02 05:17:35.000000000 +0200
--- config/sparc/little-endian.opt 2005-04-10 09:00:46.000000000 +0200
***************
*** 0 ****
--- 1,28 ----
+ ; Options for the SPARC port of the compiler
+ ;
+ ; Copyright (C) 2005 Free Software Foundation, Inc.
+ ;
+ ; This file is part of GCC.
+ ;
+ ; GCC is free software; you can redistribute it and/or modify it under
+ ; the terms of the GNU General Public License as published by the Free
+ ; Software Foundation; either version 2, or (at your option) any later
+ ; version.
+ ;
+ ; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ; License for more details.
+ ;
+ ; You should have received a copy of the GNU General Public License
+ ; along with GCC; see the file COPYING. If not, write to the Free
+ ; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ ; 02111-1307, USA.
+
+ mlittle-endian
+ Target Report RejectNegative Mask(LITTLE_ENDIAN) MaskExists
+ Generate code for little-endian
+
+ mbig-endian
+ Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+ Generate code for big-endian
*** /dev/null 2004-10-02 05:17:35.000000000 +0200
--- config/sparc/long-double-switch.opt 2005-04-09 12:55:58.000000000 +0200
***************
*** 0 ****
--- 1,28 ----
+ ; Options for the SPARC port of the compiler
+ ;
+ ; Copyright (C) 2005 Free Software Foundation, Inc.
+ ;
+ ; This file is part of GCC.
+ ;
+ ; GCC is free software; you can redistribute it and/or modify it under
+ ; the terms of the GNU General Public License as published by the Free
+ ; Software Foundation; either version 2, or (at your option) any later
+ ; version.
+ ;
+ ; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ; License for more details.
+ ;
+ ; You should have received a copy of the GNU General Public License
+ ; along with GCC; see the file COPYING. If not, write to the Free
+ ; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ ; 02111-1307, USA.
+
+ mlong-double-128
+ Target Report RejectNegative Mask(LONG_DOUBLE_128) MaskExists
+ Use 128-bit long double
+
+ mlong-double-64
+ Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
+ Use 64-bit long double