Re: [PATCH] AVR: implement HI/SI logic operations and sign/zero extension by define_insn_and_split ...

[Björn Haase <bjoern dot m dot haase at web dot de>]

> - might splitting SI/DI mode operations down to HI mode prior to reload
>   both enable the word oriented instructions addw/subw/movw/mul(word
> result) to be leveraged while also providing more register allocation
> flexibility for function calls etc, and then conditionally spit further
> after reload insertion if determined to be beneficial (as I guess I don't
> understand how once an HI mode add is split, it can easily be re-joined to
> leverage an add word instruction for example if the required registers are
> available, but not otherwise?)

Maybe, but I have doubts, whether it will be possible to extract useable 
condition codes from the expanded RTL:When expanding only towards HImode at 
expand time, gcc still would have to be able to recognize that it could 
simplify a sequence like

sub (low_word), sbc (high_word) cmp (low_word) cpc (high_word) 
conditional_branch

to 
sub (low_word), sbc (high_word) conditional_branch

. Gcc would have to overlook a span of 5 Instructions! I don't think that this 
would work. IIRC, I have read something, that combine could join up to three 
instructions. You might have a look at the combine sources.?

Yours,

Björn