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alpha options update
- From: Richard Henderson <rth at twiddle dot net>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 17 Mar 2005 02:45:06 -0800
- Subject: alpha options update
The biggest parts here are tidying some "cpu" vs "tune" confusion,
and inverting the MASK_FP bit to MASK_SOFT_FP.
Tested on alphaev67-linux.
r~
* config/alpha/alpha.opt: New file.
* config/alpha/alpha.c (alpha_tune): New. Rename all existing uses
of alpha_cpu.
(alpha_cpu_string, alpha_tune_string, alpha_tp_string,
alpha_fprm_string, alpha_fptm_string): Make static.
(alpha_tls_size_string): Remove.
(alpha_handle_option): New.
(override_options): Update for alpha_cpu/alpha_tune split.
(alpha_file_start): Likewise.
(TARGET_DEFAULT_TARGET_FLAGS): New.
(TARGET_HANDLE_OPTION): New.
* config/alpha/alpha.h (alpha_tune): Declare.
(MASK_FP, MASK_FPREGS, TARGET_FPREGS, MASK_GAS, TARGET_GAS,
MASK_IEEE_CONFORMANT, TARGET_IEEE_CONFORMANT, MASK_IEEE, TARGET_IEEE,
MASK_IEEE_WITH_INEXACT, TARGET_IEEE_WITH_INEXACT, MASK_BUILD_CONSTANTS,
TARGET_BUILD_CONSTANTS, MASK_FLOAT_VAX, TARGET_FLOAT_VAX, MASK_BWX,
TARGET_BWX, MASK_MAX, TARGET_MAX, MASK_FIX, TARGET_FIX, MASK_CIX,
TARGET_CIX, MASK_EXPLICIT_RELOCS, TARGET_EXPLICIT_RELOCS,
MASK_SMALL_DATA, TARGET_SMALL_DATA, MASK_TLS_KERNEL, TARGET_TLS_KERNEL,
MASK_SMALL_TEXT, TARGET_SMALL_TEXT, MASK_LONG_DOUBLE_128,
TARGET_LONG_DOUBLE_128, MASK_CPU_EV5, TARGET_CPU_EV5, MASK_CPU_EV6,
TARGET_CPU_EV6, MASK_SUPPORT_ARCH): Remove.
(TARGET_SWITCHES, TARGET_OPTIONS): Remove.
(TARGET_DEFAULT): Remove MASK_FP.
(TARGET_FP): Redefined based on TARGET_SOFT_FP.
(TARGET_SUPPORT_ARCH): Default on if HAVE_AS_EXPLICIT_RELOCS.
(alpha_cpu_string, alpha_tune_string, alpha_fprm_string,
alpha_fptm_string, alpha_tp_string, alpha_mlat_string,
alpha_tls_size_string): Remove.
* config/alpha/alpha.md (prefetch): Use alpha_cpu.
(attribute tune): Rename from attribute cpu.
* config/alpha/ev4.md: Update to match.
* config/alpha/ev5.md, config/alpha/ev6.md: Likewise.
* config/alpha/freebsd.h (TARGET_DEFAULT): Remove MASK_FP.
* config/alpha/linux.h (TARGET_DEFAULT): Likewise.
* config/alpha/netbsd.h (TARGET_DEFAULT): Likewise.
* config/alpha/osf5.h (TARGET_DEFAULT): Likewise.
* config/alpha/vms.h (TARGET_DEFAULT): Likewise.
Index: config/alpha/alpha.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.c,v
retrieving revision 1.410
diff -u -p -d -r1.410 alpha.c
--- config/alpha/alpha.c 14 Mar 2005 14:44:10 -0000 1.410
+++ config/alpha/alpha.c 17 Mar 2005 10:42:23 -0000
@@ -55,8 +55,11 @@ Boston, MA 02111-1307, USA. */
#include "tree-gimple.h"
/* Specify which cpu to schedule for. */
+enum processor_type alpha_tune;
+/* Which cpu we're generating code for. */
enum processor_type alpha_cpu;
+
static const char * const alpha_cpu_name[] =
{
"ev4", "ev5", "ev6"
@@ -80,13 +83,12 @@ int alpha_tls_size = 32;
/* Strings decoded into the above options. */
-const char *alpha_cpu_string; /* -mcpu= */
-const char *alpha_tune_string; /* -mtune= */
-const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
-const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
-const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
-const char *alpha_mlat_string; /* -mmemory-latency= */
-const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
+static const char *alpha_cpu_string; /* -mcpu= */
+static const char *alpha_tune_string; /* -mtune= */
+static const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
+static const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
+static const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
+static const char *alpha_mlat_string; /* -mmemory-latency= */
/* Save information from a "cmpxx" operation until the branch or scc is
emitted. */
@@ -218,36 +220,91 @@ static void unicosmk_gen_dsib (unsigned
static void unicosmk_output_ssib (FILE *, const char *);
static int unicosmk_need_dex (rtx);
+/* Implement TARGET_HANDLE_OPTION. */
+
+static bool
+alpha_handle_option (size_t code, const char *arg, int value)
+{
+ switch (code)
+ {
+ case OPT_mfp_regs:
+ if (value == 0)
+ target_flags |= MASK_SOFT_FP;
+ break;
+
+ case OPT_mieee:
+ case OPT_mieee_with_inexact:
+ target_flags |= MASK_IEEE_CONFORMANT;
+ break;
+
+ case OPT_mcpu_:
+ alpha_cpu_string = arg;
+ break;
+
+ case OPT_mtune_:
+ alpha_tune_string = arg;
+ break;
+
+ case OPT_mfp_rounding_mode_:
+ alpha_fprm_string = arg;
+ break;
+
+ case OPT_mfp_trap_mode_:
+ alpha_fptm_string = arg;
+ break;
+
+ case OPT_mtrap_precision_:
+ alpha_tp_string = arg;
+ break;
+
+ case OPT_mmemory_latency_:
+ alpha_mlat_string = arg;
+ break;
+
+ case OPT_mtls_size_:
+ if (strcmp (arg, "16") == 0)
+ alpha_tls_size = 16;
+ else if (strcmp (arg, "32") == 0)
+ alpha_tls_size = 32;
+ else if (strcmp (arg, "64") == 0)
+ alpha_tls_size = 64;
+ else
+ error ("bad value %qs for -mtls-size switch", arg);
+ break;
+ }
+
+ return true;
+}
+
/* Parse target option strings. */
void
override_options (void)
{
- int i;
static const struct cpu_table {
const char *const name;
const enum processor_type processor;
const int flags;
} cpu_table[] = {
-#define EV5_MASK (MASK_CPU_EV5)
-#define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
{ "ev4", PROCESSOR_EV4, 0 },
{ "ev45", PROCESSOR_EV4, 0 },
{ "21064", PROCESSOR_EV4, 0 },
- { "ev5", PROCESSOR_EV5, EV5_MASK },
- { "21164", PROCESSOR_EV5, EV5_MASK },
- { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
- { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
- { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
- { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
- { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
- { "ev6", PROCESSOR_EV6, EV6_MASK },
- { "21264", PROCESSOR_EV6, EV6_MASK },
- { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
- { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
+ { "ev5", PROCESSOR_EV5, 0 },
+ { "21164", PROCESSOR_EV5, 0 },
+ { "ev56", PROCESSOR_EV5, MASK_BWX },
+ { "21164a", PROCESSOR_EV5, MASK_BWX },
+ { "pca56", PROCESSOR_EV5, MASK_BWX|MASK_MAX },
+ { "21164PC",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
+ { "21164pc",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
+ { "ev6", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
+ { "21264", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
+ { "ev67", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX },
+ { "21264a", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX },
{ 0, 0, 0 }
};
+ int i;
+
/* Unicos/Mk doesn't have shared libraries. */
if (TARGET_ABI_UNICOSMK && flag_pic)
{
@@ -335,30 +392,13 @@ override_options (void)
error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string);
}
- if (alpha_tls_size_string)
- {
- if (strcmp (alpha_tls_size_string, "16") == 0)
- alpha_tls_size = 16;
- else if (strcmp (alpha_tls_size_string, "32") == 0)
- alpha_tls_size = 32;
- else if (strcmp (alpha_tls_size_string, "64") == 0)
- alpha_tls_size = 64;
- else
- error ("bad value %qs for -mtls-size switch", alpha_tls_size_string);
- }
-
- alpha_cpu
- = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
- : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
-
if (alpha_cpu_string)
{
for (i = 0; cpu_table [i].name; i++)
if (! strcmp (alpha_cpu_string, cpu_table [i].name))
{
- alpha_cpu = cpu_table [i].processor;
- target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
- | MASK_CPU_EV5 | MASK_CPU_EV6);
+ alpha_tune = alpha_cpu = cpu_table [i].processor;
+ target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
target_flags |= cpu_table [i].flags;
break;
}
@@ -371,7 +411,7 @@ override_options (void)
for (i = 0; cpu_table [i].name; i++)
if (! strcmp (alpha_tune_string, cpu_table [i].name))
{
- alpha_cpu = cpu_table [i].processor;
+ alpha_tune = cpu_table [i].processor;
break;
}
if (! cpu_table [i].name)
@@ -387,13 +427,13 @@ override_options (void)
}
if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
- && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
+ && alpha_tp != ALPHA_TP_INSN && alpha_cpu != PROCESSOR_EV6)
{
warning ("fp software completion requires -mtrap-precision=i");
alpha_tp = ALPHA_TP_INSN;
}
- if (TARGET_CPU_EV6)
+ if (alpha_cpu == PROCESSOR_EV6)
{
/* Except for EV6 pass 1 (not released), we always have precise
arithmetic traps. Which means we can do software completion
@@ -440,14 +480,14 @@ override_options (void)
};
lat = alpha_mlat_string[1] - '0';
- if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
+ if (lat <= 0 || lat > 3 || cache_latency[alpha_tune][lat-1] == -1)
{
warning ("L%d cache latency unknown for %s",
- lat, alpha_cpu_name[alpha_cpu]);
+ lat, alpha_cpu_name[alpha_tune]);
lat = 3;
}
else
- lat = cache_latency[alpha_cpu][lat-1];
+ lat = cache_latency[alpha_tune][lat-1];
}
else if (! strcmp (alpha_mlat_string, "main"))
{
@@ -1339,7 +1379,7 @@ alpha_rtx_costs (rtx x, int code, int ou
if (optimize_size)
cost_data = &alpha_rtx_cost_size;
else
- cost_data = &alpha_rtx_cost_data[alpha_cpu];
+ cost_data = &alpha_rtx_cost_data[alpha_tune];
switch (code)
{
@@ -2909,7 +2949,7 @@ alpha_split_conditional_move (enum rtx_c
/* On EV6, we've got enough shifters to make non-arithmetic shifts
viable over a longer latency cmove. On EV5, the E0 slot is a
scarce resource, and on EV4 shift has the same latency as a cmove. */
- && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
+ && (diff <= 8 || alpha_tune == PROCESSOR_EV6))
{
tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
@@ -4465,7 +4505,7 @@ alpha_adjust_cost (rtx insn, rtx link, r
static int
alpha_issue_rate (void)
{
- return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
+ return (alpha_tune == PROCESSOR_EV4 ? 2 : 4);
}
/* How many alternative schedules to try. This should be as wide as the
@@ -4479,7 +4519,7 @@ alpha_issue_rate (void)
static int
alpha_multipass_dfa_lookahead (void)
{
- return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
+ return (alpha_tune == PROCESSOR_EV6 ? 4 : 2);
}
/* Machine-specific function data. */
@@ -8774,9 +8814,9 @@ alpha_reorg (void)
&& alpha_tp != ALPHA_TP_INSN
&& flag_schedule_insns_after_reload)
{
- if (alpha_cpu == PROCESSOR_EV4)
+ if (alpha_tune == PROCESSOR_EV4)
alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
- else if (alpha_cpu == PROCESSOR_EV5)
+ else if (alpha_tune == PROCESSOR_EV5)
alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
}
}
@@ -8809,12 +8849,22 @@ alpha_file_start (void)
if (TARGET_EXPLICIT_RELOCS)
fputs ("\t.set nomacro\n", asm_out_file);
if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
- fprintf (asm_out_file,
- "\t.arch %s\n",
- TARGET_CPU_EV6 ? "ev6"
- : (TARGET_CPU_EV5
- ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
- : "ev4"));
+ {
+ const char *arch;
+
+ if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX)
+ arch = "ev6";
+ else if (TARGET_MAX)
+ arch = "pca56";
+ else if (TARGET_BWX)
+ arch = "ev56";
+ else if (alpha_cpu == PROCESSOR_EV5)
+ arch = "ev5";
+ else
+ arch = "ev4";
+
+ fprintf (asm_out_file, "\t.arch %s\n", arch);
+ }
}
#endif
@@ -10150,6 +10200,12 @@ alpha_init_libfuncs (void)
#undef TARGET_RELAXED_ORDERING
#define TARGET_RELAXED_ORDERING true
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS \
+ (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION alpha_handle_option
+
struct gcc_target targetm = TARGET_INITIALIZER;
Index: config/alpha/alpha.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.h,v
retrieving revision 1.238
diff -u -p -d -r1.238 alpha.h
--- config/alpha/alpha.h 22 Jan 2005 12:53:24 -0000 1.238
+++ config/alpha/alpha.h 17 Mar 2005 10:42:23 -0000
@@ -48,12 +48,12 @@ Boston, MA 02111-1307, USA. */
builtin_define ("__alpha_max__"); \
builtin_assert ("cpu=max"); \
} \
- if (TARGET_CPU_EV6) \
+ if (alpha_cpu == PROCESSOR_EV6) \
{ \
builtin_define ("__alpha_ev6__"); \
builtin_assert ("cpu=ev6"); \
} \
- else if (TARGET_CPU_EV5) \
+ else if (alpha_cpu == PROCESSOR_EV5) \
{ \
builtin_define ("__alpha_ev5__"); \
builtin_assert ("cpu=ev5"); \
@@ -122,6 +122,7 @@ enum processor_type
};
extern enum processor_type alpha_cpu;
+extern enum processor_type alpha_tune;
enum alpha_trap_precision
{
@@ -153,102 +154,8 @@ extern enum alpha_fp_rounding_mode alpha
extern enum alpha_fp_trap_mode alpha_fptm;
extern int alpha_tls_size;
-/* This means that floating-point support exists in the target implementation
- of the Alpha architecture. This is usually the default. */
-#define MASK_FP (1 << 0)
-#define TARGET_FP (target_flags & MASK_FP)
-
-/* This means that floating-point registers are allowed to be used. Note
- that Alpha implementations without FP operations are required to
- provide the FP registers. */
-
-#define MASK_FPREGS (1 << 1)
-#define TARGET_FPREGS (target_flags & MASK_FPREGS)
-
-/* This means that gas is used to process the assembler file. */
-
-#define MASK_GAS (1 << 2)
-#define TARGET_GAS (target_flags & MASK_GAS)
-
-/* This means that we should mark procedures as IEEE conformant. */
-
-#define MASK_IEEE_CONFORMANT (1 << 3)
-#define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
-
-/* This means we should be IEEE-compliant except for inexact. */
-
-#define MASK_IEEE (1 << 4)
-#define TARGET_IEEE (target_flags & MASK_IEEE)
-
-/* This means we should be fully IEEE-compliant. */
-
-#define MASK_IEEE_WITH_INEXACT (1 << 5)
-#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
-
-/* This means we must construct all constants rather than emitting
- them as literal data. */
-
-#define MASK_BUILD_CONSTANTS (1 << 6)
-#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
-
-/* This means we handle floating points in VAX F- (float)
- or G- (double) Format. */
-
-#define MASK_FLOAT_VAX (1 << 7)
-#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
-
-/* This means that the processor has byte and half word loads and stores
- (the BWX extension). */
-
-#define MASK_BWX (1 << 8)
-#define TARGET_BWX (target_flags & MASK_BWX)
-
-/* This means that the processor has the MAX extension. */
-#define MASK_MAX (1 << 9)
-#define TARGET_MAX (target_flags & MASK_MAX)
-
-/* This means that the processor has the FIX extension. */
-#define MASK_FIX (1 << 10)
-#define TARGET_FIX (target_flags & MASK_FIX)
-
-/* This means that the processor has the CIX extension. */
-#define MASK_CIX (1 << 11)
-#define TARGET_CIX (target_flags & MASK_CIX)
-
-/* This means use !literal style explicit relocations. */
-#define MASK_EXPLICIT_RELOCS (1 << 12)
-#define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
-
-/* This means use 16-bit relocations to .sdata/.sbss. */
-#define MASK_SMALL_DATA (1 << 13)
-#define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)
-
-/* This means emit thread pointer loads for kernel not user. */
-#define MASK_TLS_KERNEL (1 << 14)
-#define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL)
-
-/* This means use direct branches to local functions. */
-#define MASK_SMALL_TEXT (1 << 15)
-#define TARGET_SMALL_TEXT (target_flags & MASK_SMALL_TEXT)
-
-/* This means use IEEE quad-format for long double. Assumes the
- presence of the GEM support library routines. */
-#define MASK_LONG_DOUBLE_128 (1 << 16)
-#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
-
-/* This means that the processor is an EV5, EV56, or PCA56.
- Unlike alpha_cpu this is not affected by -mtune= setting. */
-#define MASK_CPU_EV5 (1 << 28)
-#define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
-
-/* Likewise for EV6. */
-#define MASK_CPU_EV6 (1 << 29)
-#define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
-
-/* This means we support the .arch directive in the assembler. Only
- defined in TARGET_CPU_DEFAULT. */
-#define MASK_SUPPORT_ARCH (1 << 30)
-#define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
+/* Invert the easy way to make options work. */
+#define TARGET_FP (!TARGET_SOFT_FP)
/* These are for target os support and cannot be changed at runtime. */
#define TARGET_ABI_WINDOWS_NT 0
@@ -283,60 +190,7 @@ extern int alpha_tls_size;
#define HAVE_AS_TLS 0
#endif
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
- { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
- {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
- {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
- {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
- N_("Do not use fp registers")}, \
- {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
- {"gas", MASK_GAS, N_("Assume GAS")}, \
- {"ieee-conformant", MASK_IEEE_CONFORMANT, \
- N_("Request IEEE-conformant math library routines (OSF/1)")}, \
- {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
- N_("Emit IEEE-conformant code, without inexact exceptions")}, \
- {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
- N_("Emit IEEE-conformant code, with inexact exceptions")}, \
- {"build-constants", MASK_BUILD_CONSTANTS, \
- N_("Do not emit complex integer constants to read-only memory")}, \
- {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
- {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
- {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
- {"no-bwx", -MASK_BWX, ""}, \
- {"max", MASK_MAX, \
- N_("Emit code for the motion video ISA extension")}, \
- {"no-max", -MASK_MAX, ""}, \
- {"fix", MASK_FIX, \
- N_("Emit code for the fp move and sqrt ISA extension")}, \
- {"no-fix", -MASK_FIX, ""}, \
- {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
- {"no-cix", -MASK_CIX, ""}, \
- {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
- N_("Emit code using explicit relocation directives")}, \
- {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \
- {"small-data", MASK_SMALL_DATA, \
- N_("Emit 16-bit relocations to the small data areas")}, \
- {"large-data", -MASK_SMALL_DATA, \
- N_("Emit 32-bit relocations to the small data areas")}, \
- {"small-text", MASK_SMALL_TEXT, \
- N_("Emit direct branches to local functions")}, \
- {"large-text", -MASK_SMALL_TEXT, ""}, \
- {"tls-kernel", MASK_TLS_KERNEL, \
- N_("Emit rdval instead of rduniq for thread pointer")}, \
- {"long-double-128", MASK_LONG_DOUBLE_128, \
- N_("Use 128-bit long double")}, \
- {"long-double-64", -MASK_LONG_DOUBLE_128, \
- N_("Use 64-bit long double")}, \
- {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \
- | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} }
-
-#define TARGET_DEFAULT MASK_FP|MASK_FPREGS
+#define TARGET_DEFAULT MASK_FPREGS
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
@@ -345,36 +199,15 @@ extern int alpha_tls_size;
#ifndef TARGET_DEFAULT_EXPLICIT_RELOCS
#ifdef HAVE_AS_EXPLICIT_RELOCS
#define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS
+#define TARGET_SUPPORT_ARCH 1
#else
#define TARGET_DEFAULT_EXPLICIT_RELOCS 0
#endif
#endif
-extern const char *alpha_cpu_string; /* For -mcpu= */
-extern const char *alpha_tune_string; /* For -mtune= */
-extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
-extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
-extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
-extern const char *alpha_mlat_string; /* For -mmemory-latency= */
-extern const char *alpha_tls_size_string; /* For -mtls-size= */
-
-#define TARGET_OPTIONS \
-{ \
- {"cpu=", &alpha_cpu_string, \
- N_("Use features of and schedule given CPU"), 0}, \
- {"tune=", &alpha_tune_string, \
- N_("Schedule given CPU"), 0}, \
- {"fp-rounding-mode=", &alpha_fprm_string, \
- N_("Control the generated fp rounding mode"), 0}, \
- {"fp-trap-mode=", &alpha_fptm_string, \
- N_("Control the IEEE trap mode"), 0}, \
- {"trap-precision=", &alpha_tp_string, \
- N_("Control the precision given to fp exceptions"), 0}, \
- {"memory-latency=", &alpha_mlat_string, \
- N_("Tune expected memory latency"), 0}, \
- {"tls-size=", &alpha_tls_size_string, \
- N_("Specify bit size of immediate TLS offsets"), 0}, \
-}
+#ifndef TARGET_SUPPORT_ARCH
+#define TARGET_SUPPORT_ARCH 0
+#endif
/* Support for a compile-time default CPU, et cetera. The rules are:
--with-cpu is ignored if -mcpu is specified.
Index: config/alpha/alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.236
diff -u -p -d -r1.236 alpha.md
--- config/alpha/alpha.md 8 Mar 2005 12:01:17 -0000 1.236
+++ config/alpha/alpha.md 17 Mar 2005 10:42:26 -0000
@@ -87,8 +87,8 @@
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in alpha.h.
-(define_attr "cpu" "ev4,ev5,ev6"
- (const (symbol_ref "alpha_cpu")))
+(define_attr "tune" "ev4,ev5,ev6"
+ (const (symbol_ref "alpha_tune")))
;; Define an insn type attribute. This is used in function unit delay
;; computations, among other purposes. For the most part, we use the names
@@ -6982,7 +6982,7 @@
[(prefetch (match_operand:DI 0 "address_operand" "p")
(match_operand:DI 1 "const_int_operand" "n")
(match_operand:DI 2 "const_int_operand" "n"))]
- "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
+ "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
{
/* Interpret "no temporal locality" as this data should be evicted once
it is used. The "evict next" alternatives load the data into the cache
Index: config/alpha/alpha.opt
===================================================================
RCS file: config/alpha/alpha.opt
diff -N config/alpha/alpha.opt
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ config/alpha/alpha.opt 17 Mar 2005 10:42:26 -0000
@@ -0,0 +1,114 @@
+msoft-float
+Target Report Mask(SOFT_FP)
+Do not use hardware fp
+
+mfp-regs
+Target Report Mask(FPREGS)
+Use fp registers
+
+mgas
+Target RejectNegative Mask(GAS)
+Assume GAS
+
+malpha-as
+Target RejectNegative InverseMask(GAS)
+Do not assume GAS
+
+mieee-conformant
+Target RejectNegative Mask(IEEE_CONFORMANT)
+Request IEEE-conformant math library routines (OSF/1)
+
+mieee
+Target Report RejectNegative Mask(IEEE)
+Emit IEEE-conformant code, without inexact exceptions
+
+mieee-with-inexact
+Target Report RejectNegative Mask(IEEE_WITH_INEXACT)
+
+mbuild-constants
+Target Report Mask(BUILD_CONSTANTS)
+Do not emit complex integer constants to read-only memory
+
+mfloat-vax
+Target Report RejectNegative Mask(FLOAT_VAX)
+Use VAX fp
+
+mfloat-ieee
+Target Report RejectNegative InverseMask(FLOAT_VAX)
+Do not use VAX fp
+
+mbwx
+Target Report Mask(BWX)
+Emit code for the byte/word ISA extension
+
+mmax
+Target Report Mask(MAX)
+Emit code for the motion video ISA extension
+
+mfix
+Target Report Mask(FIX)
+Emit code for the fp move and sqrt ISA extension
+
+mcix
+Target Report Mask(CIX)
+Emit code for the counting ISA extension
+
+mexplicit-relocs
+Target Report Mask(EXPLICIT_RELOCS)
+Emit code using explicit relocation directives
+
+msmall-data
+Target Report RejectNegative Mask(SMALL_DATA)
+Emit 16-bit relocations to the small data areas
+
+mlarge-data
+Target Report RejectNegative InverseMask(SMALL_DATA)
+Emit 32-bit relocations to the small data areas
+
+msmall-text
+Target Report RejectNegative Mask(SMALL_TEXT)
+Emit direct branches to local functions
+
+mlarge-text
+Target Report RejectNegative InverseMask(SMALL_TEXT)
+Emit indirect branches to local functions
+
+mtls-kernel
+Target Report Mask(TLS_KERNEL)
+Emit rdval instead of rduniq for thread pointer
+
+mlong-double-128
+Target Report RejectNegative Mask(LONG_DOUBLE_128)
+Use 128-bit long double
+
+mlong-double-64
+Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
+Use 64-bit long double
+
+mcpu=
+Target RejectNegative Joined
+Use features of and schedule given CPU
+
+mtune=
+Target RejectNegative Joined
+Schedule given CPU
+
+mfp-rounding-mode=
+Target RejectNegative Joined
+Control the generated fp rounding mode
+
+mfp-trap-mode=
+Target RejectNegative Joined
+Control the IEEE trap mode
+
+mtrap-precision=
+Target RejectNegative Joined
+Control the precision given to fp exceptions
+
+mmemory-latency=
+Target RejectNegative Joined
+Tune expected memory latency
+
+mtls-size=
+Target RejectNegative Joined
+Specify bit size of immediate TLS offsets
Index: config/alpha/ev4.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/ev4.md,v
retrieving revision 1.5
diff -u -p -d -r1.5 ev4.md
--- config/alpha/ev4.md 17 Oct 2004 18:09:36 -0000 1.5
+++ config/alpha/ev4.md 17 Mar 2005 10:42:27 -0000
@@ -31,41 +31,41 @@
; Assume type "multi" single issues.
(define_insn_reservation "ev4_multi" 1
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "multi"))
"ev4_ib0+ev4_ib1")
; Loads from L0 completes in three cycles. adjust_cost still factors
; in user-specified memory latency, so return 1 here.
(define_insn_reservation "ev4_ld" 1
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "ild,fld,ldsym"))
"ev4_ib01+ev4_abox")
; Stores can issue before the data (but not address) is ready.
(define_insn_reservation "ev4_ist" 1
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "ist"))
"ev4_ib1+ev4_abox")
(define_insn_reservation "ev4_fst" 1
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "fst"))
"ev4_ib0+ev4_abox")
; Branches have no delay cost, but do tie up the unit for two cycles.
(define_insn_reservation "ev4_ibr" 2
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "ibr,jsr"))
"ev4_ib1+ev4_bbox,ev4_bbox")
(define_insn_reservation "ev4_callpal" 2
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "callpal"))
"ev4_ib1+ev4_bbox,ev4_bbox")
(define_insn_reservation "ev4_fbr" 2
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "fbr"))
"ev4_ib0+ev4_bbox,ev4_bbox")
@@ -73,7 +73,7 @@
; two cycles. There are a number of exceptions.
(define_insn_reservation "ev4_iaddlog" 2
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "iadd,ilog"))
"ev4_ib0+ev4_ebox")
@@ -82,12 +82,12 @@
"ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi")
(define_insn_reservation "ev4_shiftcm" 2
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "shift,icmov"))
"ev4_ib0+ev4_ebox")
(define_insn_reservation "ev4_icmp" 2
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "icmp"))
"ev4_ib0+ev4_ebox")
@@ -102,7 +102,7 @@
; be issued exactly three cycles before an integer multiply completes".
(define_insn_reservation "ev4_imulsi" 21
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(and (eq_attr "type" "imul")
(eq_attr "opsize" "si")))
"ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox")
@@ -110,7 +110,7 @@
(define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p")
(define_insn_reservation "ev4_imuldi" 23
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(and (eq_attr "type" "imul")
(eq_attr "opsize" "!si")))
"ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox")
@@ -119,7 +119,7 @@
; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in.
(define_insn_reservation "ev4_fpop" 6
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "fadd,fmul,fcpys,fcmov"))
"ev4_ib1+ev4_fbox")
@@ -129,19 +129,19 @@
; issued exactly five or exactly six cycles before an fdiv insn completes".
(define_insn_reservation "ev4_fdivsf" 34
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(and (eq_attr "type" "fdiv")
(eq_attr "opsize" "si")))
"ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox")
(define_insn_reservation "ev4_fdivdf" 63
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(and (eq_attr "type" "fdiv")
(eq_attr "opsize" "di")))
"ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox")
; Traps don't consume or produce data.
(define_insn_reservation "ev4_misc" 1
- (and (eq_attr "cpu" "ev4")
+ (and (eq_attr "tune" "ev4")
(eq_attr "type" "misc"))
"ev4_ib1")
Index: config/alpha/ev5.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/ev5.md,v
retrieving revision 1.6
diff -u -p -d -r1.6 ev5.md
--- config/alpha/ev5.md 17 Oct 2004 18:09:36 -0000 1.6
+++ config/alpha/ev5.md 17 Mar 2005 10:42:27 -0000
@@ -30,7 +30,7 @@
; Assume type "multi" single issues.
(define_insn_reservation "ev5_multi" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "multi"))
"ev5_e0+ev5_e1+ev5_fa+ev5_fm")
@@ -42,55 +42,55 @@
(exclusion_set "ev5_l0,ev5_l1" "ev5_st")
(define_insn_reservation "ev5_st" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "ist,fst"))
"ev5_e0+ev5_st")
; Loads from L0 complete in two cycles. adjust_cost still factors
; in user-specified memory latency, so return 1 here.
(define_insn_reservation "ev5_ld" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "ild,fld,ldsym"))
"ev5_e01+ev5_ld")
; Integer branches slot only to E1.
(define_insn_reservation "ev5_ibr" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "ibr"))
"ev5_e1")
(define_insn_reservation "ev5_callpal" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "callpal"))
"ev5_e1")
(define_insn_reservation "ev5_jsr" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "jsr"))
"ev5_e1")
(define_insn_reservation "ev5_shift" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "shift"))
"ev5_e0")
(define_insn_reservation "ev5_mvi" 2
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "mvi"))
"ev5_e0")
(define_insn_reservation "ev5_cmov" 2
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "icmov"))
"ev5_e01")
(define_insn_reservation "ev5_iadd" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "iadd"))
"ev5_e01")
(define_insn_reservation "ev5_ilogcmp" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "ilog,icmp"))
"ev5_e01")
@@ -101,19 +101,19 @@
; to E0 exactly two cycles before an integer multiply completes".
(define_insn_reservation "ev5_imull" 8
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(and (eq_attr "type" "imul")
(eq_attr "opsize" "si")))
"ev5_e0+ev5_imul,ev5_imul*3,nothing,ev5_e0")
(define_insn_reservation "ev5_imulq" 12
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(and (eq_attr "type" "imul")
(eq_attr "opsize" "di")))
"ev5_e0+ev5_imul,ev5_imul*7,nothing,ev5_e0")
(define_insn_reservation "ev5_imulh" 14
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(and (eq_attr "type" "imul")
(eq_attr "opsize" "udi")))
"ev5_e0+ev5_imul,ev5_imul*7,nothing*3,ev5_e0")
@@ -139,22 +139,22 @@
; Similarly for the FPU we have two asymmetric units.
(define_insn_reservation "ev5_fadd" 4
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "fadd,fcmov"))
"ev5_fa")
(define_insn_reservation "ev5_fbr" 1
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "fbr"))
"ev5_fa")
(define_insn_reservation "ev5_fcpys" 4
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "fcpys"))
"ev5_fam")
(define_insn_reservation "ev5_fmul" 4
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "fmul"))
"ev5_fm")
@@ -170,14 +170,14 @@
; the other, i.e. ev5_fcpys.
(define_insn_reservation "ev5_fdivsf" 15
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(and (eq_attr "type" "fdiv")
(eq_attr "opsize" "si")))
; "ev5_fa+ev5_fdiv,ev5_fdiv*9,ev5_fa+ev5_fdiv,ev5_fdiv*4"
"ev5_fa+ev5_fdiv,ev5_fdiv*14")
(define_insn_reservation "ev5_fdivdf" 22
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(and (eq_attr "type" "fdiv")
(eq_attr "opsize" "di")))
; "ev5_fa+ev5_fdiv,ev5_fdiv*17,ev5_fa+ev5_fdiv,ev5_fdiv*4"
@@ -185,6 +185,6 @@
; Traps don't consume or produce data; rpcc is latency 2 if we ever add it.
(define_insn_reservation "ev5_misc" 2
- (and (eq_attr "cpu" "ev5")
+ (and (eq_attr "tune" "ev5")
(eq_attr "type" "misc"))
"ev5_e0")
Index: config/alpha/ev6.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/ev6.md,v
retrieving revision 1.5
diff -u -p -d -r1.5 ev6.md
--- config/alpha/ev6.md 17 Oct 2004 18:09:36 -0000 1.5
+++ config/alpha/ev6.md 17 Mar 2005 10:42:27 -0000
@@ -45,26 +45,26 @@
; Assume type "multi" single issues.
(define_insn_reservation "ev6_multi" 1
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "multi"))
"ev6_u0+ev6_u1+ev6_l0+ev6_l1+ev6_fa+ev6_fm+ev6_fst0+ev6_fst1")
; Integer loads take at least 3 clocks, and only issue to lower units.
; adjust_cost still factors in user-specified memory latency, so return 1 here.
(define_insn_reservation "ev6_ild" 1
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "ild,ldsym"))
"ev6_l")
(define_insn_reservation "ev6_ist" 1
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "ist"))
"ev6_l")
; FP loads take at least 4 clocks. adjust_cost still factors
; in user-specified memory latency, so return 2 here.
(define_insn_reservation "ev6_fld" 2
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "fld"))
"ev6_l")
@@ -75,99 +75,99 @@
; file and the insn retired.
(define_insn_reservation "ev6_fst" 3
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "fst"))
"ev6_fst,nothing,ev6_l")
; Arithmetic goes anywhere.
(define_insn_reservation "ev6_arith" 1
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "iadd,ilog,icmp"))
"ev6_ebox")
; Motion video insns also issue only to U0, and take three ticks.
(define_insn_reservation "ev6_mvi" 3
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "mvi"))
"ev6_u0")
; Shifts issue to upper units.
(define_insn_reservation "ev6_shift" 1
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "shift"))
"ev6_u")
; Multiplies issue only to U1, and all take 7 ticks.
(define_insn_reservation "ev6_imul" 7
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "imul"))
"ev6_u1")
; Conditional moves decompose into two independent primitives, each taking
; one cycle. Since ev6 is out-of-order, we can't see anything but two cycles.
(define_insn_reservation "ev6_icmov" 2
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "icmov"))
"ev6_ebox,ev6_ebox")
; Integer branches issue to upper units
(define_insn_reservation "ev6_ibr" 1
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "ibr,callpal"))
"ev6_u")
; Calls only issue to L0.
(define_insn_reservation "ev6_jsr" 1
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "jsr"))
"ev6_l0")
; Ftoi/itof only issue to lower pipes.
(define_insn_reservation "ev6_itof" 3
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "itof"))
"ev6_l")
(define_insn_reservation "ev6_ftoi" 3
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "ftoi"))
"ev6_fst,nothing,ev6_l")
(define_insn_reservation "ev6_fmul" 4
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "fmul"))
"ev6_fm")
(define_insn_reservation "ev6_fadd" 4
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "fadd,fcpys,fbr"))
"ev6_fa")
(define_insn_reservation "ev6_fcmov" 8
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(eq_attr "type" "fcmov"))
"ev6_fa,nothing*3,ev6_fa")
(define_insn_reservation "ev6_fdivsf" 12
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(and (eq_attr "type" "fdiv")
(eq_attr "opsize" "si")))
"ev6_fa*9")
(define_insn_reservation "ev6_fdivdf" 15
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(and (eq_attr "type" "fdiv")
(eq_attr "opsize" "di")))
"ev6_fa*12")
(define_insn_reservation "ev6_sqrtsf" 18
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(and (eq_attr "type" "fsqrt")
(eq_attr "opsize" "si")))
"ev6_fa*15")
(define_insn_reservation "ev6_sqrtdf" 33
- (and (eq_attr "cpu" "ev6")
+ (and (eq_attr "tune" "ev6")
(and (eq_attr "type" "fsqrt")
(eq_attr "opsize" "di")))
"ev6_fa*30")
Index: config/alpha/freebsd.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/freebsd.h,v
retrieving revision 1.19
diff -u -p -d -r1.19 freebsd.h
--- config/alpha/freebsd.h 7 May 2004 03:45:01 -0000 1.19
+++ config/alpha/freebsd.h 17 Mar 2005 10:42:27 -0000
@@ -75,7 +75,7 @@ Boston, MA 02111-1307, USA. */
#define TARGET_ELF 1
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS)
+#define TARGET_DEFAULT (MASK_FPREGS | MASK_GAS)
#undef HAS_INIT_SECTION
Index: config/alpha/linux.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/linux.h,v
retrieving revision 1.42
diff -u -p -d -r1.42 linux.h
--- config/alpha/linux.h 11 Nov 2004 03:17:59 -0000 1.42
+++ config/alpha/linux.h 17 Mar 2005 10:42:27 -0000
@@ -22,7 +22,7 @@ the Free Software Foundation, 59 Temple
Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS)
+#define TARGET_DEFAULT (MASK_FPREGS | MASK_GAS)
#define TARGET_OS_CPP_BUILTINS() \
do { \
Index: config/alpha/netbsd.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/netbsd.h,v
retrieving revision 1.22
diff -u -p -d -r1.22 netbsd.h
--- config/alpha/netbsd.h 17 Oct 2004 18:09:36 -0000 1.22
+++ config/alpha/netbsd.h 17 Mar 2005 10:42:27 -0000
@@ -20,7 +20,7 @@ the Free Software Foundation, 59 Temple
Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS)
+#define TARGET_DEFAULT (MASK_FPREGS | MASK_GAS)
#define TARGET_OS_CPP_BUILTINS() \
do { \
Index: config/alpha/osf5.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/osf5.h,v
retrieving revision 1.10
diff -u -p -d -r1.10 osf5.h
--- config/alpha/osf5.h 6 Mar 2004 18:48:51 -0000 1.10
+++ config/alpha/osf5.h 17 Mar 2005 10:42:27 -0000
@@ -20,7 +20,7 @@
/* Tru64 5.1 uses IEEE QUAD format. */
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT MASK_FP | MASK_FPREGS | MASK_LONG_DOUBLE_128
+#define TARGET_DEFAULT (MASK_FPREGS | MASK_LONG_DOUBLE_128)
/* In Tru64 UNIX V5.1, Compaq introduced a new assembler
(/usr/lib/cmplrs/cc/adu) which currently (versions between 3.04.29 and
Index: config/alpha/vms.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/vms.h,v
retrieving revision 1.84
diff -u -p -d -r1.84 vms.h
--- config/alpha/vms.h 30 Dec 2004 03:07:39 -0000 1.84
+++ config/alpha/vms.h 17 Mar 2005 10:42:27 -0000
@@ -42,7 +42,7 @@ Boston, MA 02111-1307, USA. */
} while (0)
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP|MASK_FPREGS|MASK_GAS)
+#define TARGET_DEFAULT (MASK_FPREGS|MASK_GAS)
#undef TARGET_ABI_OPEN_VMS
#define TARGET_ABI_OPEN_VMS 1