Fix remaining warnings in sparc.md

[Eric Botcazou <ebotcazou at libertysurf dot fr>]

The last 2 warnings are about missing modes for the load_pcrel_sym pattern.

Fixed by switched it (as well as the save_register_window pattern) to using 
the mode macro facility.

Bootstrapped/regtested on sparc-sun-solaris2.8 (but it introduces the pdist.c 
failure mentioned in the previous mail), applied to mainline.


2005-01-18  Eric Botcazou  <ebotcazou@libertysurf.fr>

	* config/sparc/sparc.c (load_pic_register): Emit the appropriate
	variant of the load_pcrel_sym pattern.
	* config/sparc/sparc.md (P macro): Move to the top.
	(load_pcrel_sym): Macroize using P.
	(save_register_window): Likewise.


-- 
Eric Botcazou

Index: config/sparc/sparc.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.c,v
retrieving revision 1.352
diff -u -p -r1.352 sparc.c
--- config/sparc/sparc.c	3 Jan 2005 08:23:58 -0000	1.352
+++ config/sparc/sparc.c	18 Jan 2005 07:48:58 -0000
@@ -3981,8 +3981,12 @@ load_pic_register (void)
   add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
 
   flag_pic = 0;
-  emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
-				 add_pc_to_pic_symbol));
+  if (TARGET_ARCH64)
+    emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
+				     add_pc_to_pic_symbol));
+  else
+    emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
+				     add_pc_to_pic_symbol));
   flag_pic = orig_flag_pic;
 
   /* Need to emit this whether or not we obey regdecls,
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.md,v
retrieving revision 1.224
diff -u -p -r1.224 sparc.md
--- config/sparc/sparc.md	4 Jan 2005 19:03:45 -0000	1.224
+++ config/sparc/sparc.md	18 Jan 2005 07:49:00 -0000
@@ -68,6 +68,8 @@
    (UNSPECV_SAVEW		6)
   ])
 
+(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+
 ;; The upper 32 fp regs on the v9 can't hold SFmode values.  To deal with this
 ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip.  The name
 ;; is a bit of a misnomer as it covers all 64 fp regs.  The corresponding
@@ -1694,11 +1696,11 @@
 ;; value subject to a PC-relative relocation.  Operand 2 is a helper function
 ;; that adds the PC value at the call point to operand 0.
 
-(define_insn "load_pcrel_sym"
-  [(set (match_operand 0 "register_operand" "=r")
-	(unspec [(match_operand 1 "symbolic_operand" "")
-		 (match_operand 2 "call_operand_address" "")] UNSPEC_LOAD_PCREL_SYM))
-   (clobber (reg:SI 15))]
+(define_insn "load_pcrel_sym<P:mode>"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(unspec:P [(match_operand:P 1 "symbolic_operand" "")
+		   (match_operand:P 2 "call_operand_address" "")] UNSPEC_LOAD_PCREL_SYM))
+   (clobber (reg:P 15))]
   ""
 {
   if (flag_delayed_branch)
@@ -7721,23 +7723,12 @@
 ;;  (set (%sp) (unspec_volatile [(%sp) (-frame_size)] UNSPECV_SAVEW))
 ;;  (set (%i7) (%o7))]
 
-(define_insn "save_register_windowdi"
-  [(set (reg:DI 30) (reg:DI 14))
-   (set (reg:DI 14) (unspec_volatile:DI [(reg:DI 14)
-					 (match_operand:DI 0 "arith_operand" "rI")]
-				        UNSPECV_SAVEW))
-   (set (reg:DI 31) (reg:DI 15))]
-  "TARGET_ARCH64"
-  "save\t%%sp, %0, %%sp"
-  [(set_attr "type" "savew")])
-
-(define_insn "save_register_windowsi"
-  [(set (reg:SI 30) (reg:SI 14))
-   (set (reg:SI 14) (unspec_volatile:SI [(reg:SI 14)
-					 (match_operand:SI 0 "arith_operand" "rI")]
-				        UNSPECV_SAVEW))
-   (set (reg:SI 31) (reg:SI 15))]
-  "!TARGET_ARCH64"
+(define_insn "save_register_window<P:mode>"
+  [(set (reg:P 30) (reg:P 14))
+   (set (reg:P 14) (unspec_volatile:P [(reg:P 14)
+				       (match_operand:P 0 "arith_operand" "rI")] UNSPECV_SAVEW))
+   (set (reg:P 31) (reg:P 15))]
+  ""
   "save\t%%sp, %0, %%sp"
   [(set_attr "type" "savew")])
 
@@ -9103,8 +9094,6 @@
   [(set_attr "type" "fga")
    (set_attr "fptype" "double")])
 
-(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
-
 (define_insn "alignaddr<P:mode>_vis"
   [(set (match_operand:P 0 "register_operand" "=r")
         (unspec:P [(match_operand:P 1 "reg_or_0_operand" "rJ")