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[altivec]: More mode macros
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: Aldy Hernandez <aldyh at redhat dot com>, David Edelsohn <dje at watson dot ibm dot com>
- Date: Fri, 19 Nov 2004 10:00:31 +0000
- Subject: [altivec]: More mode macros
- Organization: Codesourcery LLC
This patch adds more uses of the mode macros. I replace the individual
add, sub, and, ior, xor, smin, smax, umin, umax with mode macro versions.
I also moved some of the instructions around so that add & sub are adjacent
and all the logical ops are together. I also added mode macro
versions of andc and nor.
When doing this I noticed that the recently canonicalized altivec_vandc
insn changed the semantics of builtin_altivec_vandc. Before the
recent change, that builtin computed arg1 & ~arg2, after the change it
it computed ~arg1 & arg2. Thus I inserted an expander to restore the
original semantics.
booted and tested on powerpc-unknown-linux-gnu, ok?
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
2004-11-19 Nathan Sidwell <nathan@codesourcery.com>
* config/rs6000/altivec.md (VI_char): New mode attribute.
(addv16qi3, addv8hi3, addv4ai3): Replace with ...
(add<mode>3): ... this.
(subv16qi3, subv8hi3, subv4ai3): Replace with ...
(sub<mode>3): ... this.
(smaxv16qi3, smaxv8hi3, smaxv4ai3): Replace with ...
(smax<mode>3): ... this.
(sminv16qi3, sminv8hi3, sminv4ai3): Replace with ...
(smin<mode>3): ... this.
(umaxv16qi3, umaxv8hi3, umaxv4ai3): Replace with ...
(umax<mode>3): ... this.
(uminv16qi3, uminv8hi3, uminv4ai3): Replace with ...
(umin<mode>3): ... this.
(andv16qi3, andv8hi3, andv4ai3): Replace with ...
(and<mode>3): ... this.
(iorv16qi3, iorv8hi3, iorv4ai3): Replace with ...
(ior<mode>3): ... this.
(xorv16qi3, xorv8hi3, xorv4ai3): Replace with ...
(xor<mode>3): ... this.
(andv16qi3, andv8hi3, andv4ai3): Replace with ...
(and<mode>3): ... this.
(iorv16qi3, iorv8hi3, iorv4ai3): Replace with ...
(ior<mode>3): ... this.
(altivec_vnor): Replace with ...
(altivec_nor<mode>): ... this.
(one_cmplv16qi2, one_cmplv8hi2, one_complv4ai2): Replace with ...
(one_cmpl<mode>2): ... this.
(altivec_vandc): New expander.
(*andc<mode>3): New insn.
* config/rs6000/rs6000.c (bdesc_2arg): Adjust for new insn names.
Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.27
diff -c -3 -p -r1.27 altivec.md
*** config/rs6000/altivec.md 18 Nov 2004 15:52:22 -0000 1.27
--- config/rs6000/altivec.md 18 Nov 2004 18:11:46 -0000
***************
*** 53,58 ****
--- 53,60 ----
;; Vec modes, pity mode macros are not composable
(define_mode_macro V [V4SI V8HI V16QI V4SF])
+ (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
+
;; Generic LVX load instruction.
(define_insn "altivec_lvx_<mode>"
[(set (match_operand:V 0 "altivec_register_operand" "=v")
***************
*** 218,245 ****
;; Simple binary operations.
! (define_insn "addv16qi3"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
! "TARGET_ALTIVEC"
! "vaddubm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "addv8hi3"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
! "TARGET_ALTIVEC"
! "vadduhm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "addv4si3"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vadduwm %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "addv4sf3"
--- 220,232 ----
;; Simple binary operations.
! ;; add
! (define_insn "add<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (plus:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vaddu<VI_char>m %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "addv4sf3"
***************
*** 312,349 ****
"vaddsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "andv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (and:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vand %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "andv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (and:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vand %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "andv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vand %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vandc"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (and:V4SI (not:V4SI (match_operand:V4SI 1 "register_operand" "v"))
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vandc %0,%2,%1"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vavgub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
--- 299,384 ----
"vaddsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
! ;; sub
! (define_insn "sub<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (minus:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
! "TARGET_ALTIVEC"
! "vsubu<VI_char>m %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "subv4sf3"
! [(set (match_operand:V4SF 0 "register_operand" "=v")
! (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")))]
! "TARGET_ALTIVEC"
! "vsubfp %0,%1,%2"
! [(set_attr "type" "vecfloat")])
!
! (define_insn "altivec_vsubcuw"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 124))]
! "TARGET_ALTIVEC"
! "vsubcuw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsububs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 125))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsububs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsubsbs"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 126))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vsubsbs %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsubuhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 127))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsubuhs %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsubshs"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 128))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vsubshs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsubuws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 129))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsubuws %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsubsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 130))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsubsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
+ ;;
(define_insn "altivec_vavgub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
***************
*** 608,667 ****
"vmsumshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
! (define_insn "umaxv16qi3"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
! "TARGET_ALTIVEC"
! "vmaxub %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "smaxv16qi3"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxsb %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "umaxv8hi3"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxuh %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "smaxv8hi3"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxsh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "umaxv4si3"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxuw %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "smaxv4si3"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxsw %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "smaxv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxfp %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vmhaddshs"
--- 643,696 ----
"vmsumshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
! ;; max
! (define_insn "umax<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (umax:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxu<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "smax<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (smax:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxs<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "smaxv4sf3"
! [(set (match_operand:V4SF 0 "register_operand" "=v")
! (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmaxfp %0,%1,%2"
! [(set_attr "type" "veccmp")])
! (define_insn "umin<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (umin:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vminu<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "smin<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (smin:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vmins<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "sminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vminfp %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vmhaddshs"
***************
*** 801,862 ****
"vmrglw %0,%1,%2"
[(set_attr "type" "vecperm")])
- (define_insn "uminv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vminub %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "sminv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vminsb %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "uminv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vminuh %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "sminv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vminsh %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "uminv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vminuw %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "sminv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vminsw %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "sminv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=v")
- (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
- (match_operand:V4SF 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vminfp %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
(define_insn "altivec_vmuleub"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
--- 830,835 ----
***************
*** 921,977 ****
"vmulosh %0,%1,%2"
[(set_attr "type" "veccomplex")])
! (define_insn "altivec_vnor"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v"))))]
! "TARGET_ALTIVEC"
! "vnor %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "one_cmplv16qi2"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (not:V16QI (match_operand:V16QI 1 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vnor %0,%1,%1"
[(set_attr "type" "vecsimple")])
!
! (define_insn "one_cmplv8hi2"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (not:V8HI (match_operand:V8HI 1 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vnor %0,%1,%1"
[(set_attr "type" "vecsimple")])
!
! (define_insn "one_cmplv4si2"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (not:V4SI (match_operand:V4SI 1 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vnor %0,%1,%1"
[(set_attr "type" "vecsimple")])
! (define_insn "iorv16qi3"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (ior:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vor %0,%1,%2"
[(set_attr "type" "vecsimple")])
!
! (define_insn "iorv8hi3"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (ior:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vor %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "iorv4si3"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vor %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vpkuhum"
--- 894,955 ----
"vmulosh %0,%1,%2"
[(set_attr "type" "veccomplex")])
!
! ;; logical ops
!
! (define_insn "and<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (and:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vand %0,%1,%2"
[(set_attr "type" "vecsimple")])
!
! (define_insn "ior<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (ior:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vor %0,%1,%2"
[(set_attr "type" "vecsimple")])
!
! (define_insn "xor<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (xor:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vxor %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "one_cmpl<mode>2"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (not:VI (match_operand:VI 1 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vnor %0,%1,%1"
[(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_nor<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v"))))]
"TARGET_ALTIVEC"
! "vnor %0,%1,%2"
[(set_attr "type" "vecsimple")])
! ;; builtin_altivec_vandc (a, b) computes a & ~b, gcc's
! ;; canonicalization of that has the operands the other way round
! (define_expand "altivec_vandc"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (and:V4SI (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))
! (match_operand:V4SI 1 "register_operand" "v")))]
! "TARGET_ALTIVEC")
!
! (define_insn "*andc<mode>3"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (and:VI (not:VI (match_operand:VI 1 "register_operand" "v"))
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vandc %0,%2,%1"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vpkuhum"
***************
*** 1206,1305 ****
"vsro %0,%1,%2"
[(set_attr "type" "vecperm")])
- (define_insn "subv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vsububm %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "subv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vsubuhm %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "subv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vsubuwm %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "subv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=v")
- (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
- (match_operand:V4SF 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vsubfp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
-
- (define_insn "altivec_vsubcuw"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")] 124))]
- "TARGET_ALTIVEC"
- "vsubcuw %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "altivec_vsububs"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")] 125))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
- "TARGET_ALTIVEC"
- "vsububs %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "altivec_vsubsbs"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")] 126))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
- "TARGET_ALTIVEC"
- "vsubsbs %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "altivec_vsubuhs"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")] 127))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
- "TARGET_ALTIVEC"
- "vsubuhs %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "altivec_vsubshs"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")] 128))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
- "TARGET_ALTIVEC"
- "vsubshs %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "altivec_vsubuws"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")] 129))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
- "TARGET_ALTIVEC"
- "vsubuws %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "altivec_vsubsws"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")] 130))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
- "TARGET_ALTIVEC"
- "vsubsws %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
(define_insn "altivec_vsum4ubs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
--- 1184,1189 ----
***************
*** 1345,1376 ****
"vsumsws %0,%1,%2"
[(set_attr "type" "veccomplex")])
- ;; Vector xor's
- (define_insn "xorv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vxor %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "xorv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (xor:V8HI (match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vxor %0,%1,%2"
- [(set_attr "type" "vecsimple")])
-
- (define_insn "xorv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (xor:V16QI (match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")))]
- "TARGET_ALTIVEC"
- "vxor %0,%1,%2"
- [(set_attr "type" "vecsimple")])
- ;; End of vector xor's
-
(define_insn "altivec_vspltb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(vec_duplicate:V16QI
--- 1229,1234 ----
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.745
diff -c -3 -p -r1.745 rs6000.c
*** config/rs6000/rs6000.c 18 Nov 2004 15:52:20 -0000 1.745
--- config/rs6000/rs6000.c 18 Nov 2004 18:12:25 -0000
*************** static struct builtin_description bdesc_
*** 6142,6148 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
{ MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
--- 6142,6148 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
! { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
{ MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },