Re: [patch] extend.texi MIPS PS/3D Support

["Chao-ying Fu" <fu at mips dot com>]

Hello,

One question is as follows.  The current MIPS64 architecture doesn't have
SIMD integer instructions.  But, the vectorizer still vectorized the
following C example and generated an incorrect code (daddu $2,$2,$3).  How
do we disable the vectorization for the integer mode?  Thanks!

Regards,
Chao-ying

<122> # cat vect2.c
#define N 16

void ibar (int *);
int a[N];
int b[N];
int c[N];

/* multiple loops */
foo (int n)
{
  int i;

  /* Vectorizable.  */
  for (i = 0; i < N; i++){
    a[i] = b[i]+c[i];
  }

  ibar (a);
}

<123> #
mipsisa64-elf-gcc -O2 -mips64 -mpaired-single -ftree-vectorize -fdump-tree-v
ect-stats -S vect2.c
<124> # cat vect2.s
 .file 1 "vect2.c"
 .section .mdebug.eabi64
 .section .gcc_compiled_long64
 .previous
 .text
 .align 2
 .align 3
 .globl foo
 .ent foo
foo:
 .frame $sp,0,$31  # vars= 0, regs= 0/0, args= 0, gp= 0
 .mask 0x00000000,0
 .fmask 0x00000000,0
 .set noreorder
 .set nomacro

 lui $10,%hi(a)
 lui $2,%hi(b)
 lui $3,%hi(c)
 daddiu $7,$2,%lo(b)
 daddiu $6,$3,%lo(c)
 daddiu $5,$10,%lo(a)
 move $8,$0
 li $9,16   # 0x10
 .align 3
$L2:
 ld $2,0($7)
 ld $3,0($6)
 addiu $4,$8,1
 daddiu $7,$7,8
 daddu $2,$2,$3 <--------------------
 sd $2,0($5)
 daddiu $6,$6,8
 daddiu $5,$5,8
 bne $9,$4,$L2
 move $8,$4

 j ibar
 daddiu $4,$10,%lo(a)

 .set macro
 .set reorder
 .end foo
 .size foo, .-foo

 .comm c,64,8

 .comm b,64,8

 .comm a,64,8
 .ident "GCC: (GNU) 4.0.0 20040927 (experimental)"

<125> # cat vect2.c.t50.vect

;; Function foo (foo)


loop at vect2.c:15: LOOP VECTORIZED.

vectorized 1 loops in function.
NOTE: no flow-sensitive alias info for vect_pb.2_10 in vect_var_.1_2 =
*vect_pb.2_10;
NOTE: no flow-sensitive alias info for vect_pc.8_27 in vect_var_.7_28 =
*vect_pc.8_27;
NOTE: no flow-sensitive alias info for vect_pa.14_35 in *vect_pa.14_35 =
vect_var_.13_29;

DFA Statistics for foo

---------------------------------------------------------
                                Number of        Memory
                                instances         used
---------------------------------------------------------
Referenced variables                     27        108b
Statements annotated                      0          0b
Variables annotated                       0          0b
USE operands                              0          0b
DEF operands                              0          0b
VUSE operands                             0          0b
V_MAY_DEF operands                        0          0b
V_MUST_DEF operands                       0          0b
PHI nodes                                 6        312b
PHI arguments                            12        144b
---------------------------------------------------------
Total memory used by DFA/SSA data                  564b
---------------------------------------------------------

Average number of arguments per PHI node: 2.0 (max: 2)


Hash table statistics:
    def_blocks: size 31, 3 elements, 0.333333 collision/search ratio


DFA Statistics for foo

---------------------------------------------------------
                                Number of        Memory
                                instances         used
---------------------------------------------------------
Referenced variables                     27        108b
Statements annotated                      0          0b
Variables annotated                       0          0b
USE operands                              0          0b
DEF operands                              0          0b
VUSE operands                             0          0b
V_MAY_DEF operands                        0          0b
V_MUST_DEF operands                       0          0b
PHI nodes                                 7        364b
PHI arguments                            13        156b
---------------------------------------------------------
Total memory used by DFA/SSA data                  628b
---------------------------------------------------------

Average number of arguments per PHI node: 1.9 (max: 2)


Hash table statistics:
    def_blocks: size 61, 1 elements, 0.000000 collision/search ratio

foo (n)
{
  int ivtmp.19;
  int update.18;
  int ivtmp.17;
  int * vect_pa.16;
  int newinit.15;
  <unnamed type> * vect_pa.14;
  <unnamed type> vect_var_.13;
  int update.12;
  int ivtmp.11;
  int * vect_pc.10;
  int newinit.9;
  <unnamed type> * vect_pc.8;
  <unnamed type> vect_var_.7;
  int update.6;
  int ivtmp.5;
  int * vect_pb.4;
  int newinit.3;
  <unnamed type> * vect_pb.2;
  <unnamed type> vect_var_.1;
  int i;
  int D.1172;
  int D.1171;
  int D.1170;
  int i.0;

<bb 0>:

<L6>:;
  vect_pb.4_13 = &b[0];
  vect_pb.2_3 = (<unnamed type> *) vect_pb.4_13;
  vect_pc.10_1 = &c[0];
  vect_pc.8_23 = (<unnamed type> *) vect_pc.10_1;
  vect_pa.16_30 = &a[0];
  vect_pa.14_31 = (<unnamed type> *) vect_pa.16_30;

  # ivtmp.19_36 = PHI <0(4), ivtmp.19_37(3)>;
  # ivtmp.17_32 = PHI <0(4), ivtmp.17_33(3)>;
  # ivtmp.11_24 = PHI <0(4), ivtmp.11_25(3)>;
  # ivtmp.5_22 = PHI <0(4), ivtmp.5_21(3)>;
  # i_20 = PHI <0(4), i_17(3)>;
<L0>:;
  update.6_18 = ivtmp.5_22 * 8;
  vect_pb.2_10 = vect_pb.2_3 + update.6_18;
  vect_var_.1_2 = *vect_pb.2_10;
  ivtmp.5_21 = ivtmp.5_22 + 1;
  D.1170_12 = b[i_20];
  update.12_26 = ivtmp.11_24 * 8;
  vect_pc.8_27 = vect_pc.8_23 + update.12_26;
  vect_var_.7_28 = *vect_pc.8_27;
  ivtmp.11_25 = ivtmp.11_24 + 1;
  D.1171_14 = c[i_20];
  vect_var_.13_29 = vect_var_.1_2 + vect_var_.7_28;
  D.1172_15 = D.1170_12 + D.1171_14;
  update.18_34 = ivtmp.17_32 * 8;
  vect_pa.14_35 = vect_pa.14_31 + update.18_34;
  *vect_pa.14_35 = vect_var_.13_29;
  ivtmp.17_33 = ivtmp.17_32 + 1;
  i_17 = i_20 + 1;
  ivtmp.19_37 = ivtmp.19_36 + 1;
  if (ivtmp.19_37 < 16) goto <L5>; else goto <L2>;

<L5>:;
  goto <bb 1> (<L0>);

<L2>:;
  ibar (&a);
  return;

}


----- Original Message ----- 
From: "Richard Sandiford" <rsandifo@redhat.com>
To: "Chao-ying Fu" <fu@mips.com>
Cc: "Dorit Naishlos" <DORIT@il.ibm.com>; <dpatel@apple.com>;
<gcc-patches@gcc.gnu.org>; "Gerald Pfeifer" <gerald@pfeifer.com>; "Giovanni
Bajo" <giovannibajo@libero.it>; "Stephens, Nigel" <nigel@mercury.mips.com>;
"Thekkath, Radhika" <radhika@mercury.mips.com>; "Uhler, Mike"
<uhler@mercury.mips.com>; "Jim Wilson" <wilson@specifixinc.com>
Sent: Friday, September 24, 2004 11:43 PM
Subject: Re: [patch] extend.texi MIPS PS/3D Support


> "Chao-ying Fu" <fu@mips.com> writes:
> > After running "cvs update" and building again today, I can compile the
code.
> > But the output assembly is wrong with
> > "<ANYF:loadx>    $f0,$9($2)" and "<ANYF:storex>   $f0,$8($2)" in it.
>
> OK, I've checked in the patch below to fix that.  Tested by running
> mips.exp for mipsisa64-elf before and after the patch (which is the
> only current test of paired-single support).  Committed to head.
> I didn't install a testcase since this would be covered by existing
> tests once autovectorisation is enabled.
>
> WRT defining UNITS_PER_SIMD_WORD: I'd like that patch to go in, but
> it would need to be run against the vectorisation testsuite first
> (--target_board mipsisa64-elf/-mpaired-single).
>
> Richard
>
>
> * config/mips/mips.md (loadx, storex): Define for V2SF.
>
> Index: config/mips/mips.md
> ===================================================================
> RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
> retrieving revision 1.307
> diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.307 mips.md
> *** config/mips/mips.md 20 Sep 2004 06:54:52 -0000 1.307
> --- config/mips/mips.md 25 Sep 2004 06:32:35 -0000
> *************** (define_mode_attr load [(SI "lw") (DI "l
> *** 355,362 ****
>   (define_mode_attr store [(SI "sw") (DI "sd")])
>
>   ;; Similarly for MIPS IV indexed FPR loads and stores.
> ! (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1")])
> ! (define_mode_attr storex [(SF "swxc1") (DF "sdxc1")])
>
>   ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
>   ;; are different.  Some forms of unextended addiu have an 8-bit
immediate
> --- 355,362 ----
>   (define_mode_attr store [(SI "sw") (DI "sd")])
>
>   ;; Similarly for MIPS IV indexed FPR loads and stores.
> ! (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
> ! (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
>
>   ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
>   ;; are different.  Some forms of unextended addiu have an 8-bit
immediate
>