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[PATCH, committed] POWER store latency
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 01 Sep 2004 21:56:03 -0400
- Subject: [PATCH, committed] POWER store latency
* config/rs6000/power4.md: Increase store latency to 12.
* config/rs6000/power5.md: Same.
Index: power4.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/power4.md,v
retrieving revision 1.15
diff -c -p -r1.15 power4.md
*** power4.md 8 Jul 2003 01:45:29 -0000 1.15
--- power4.md 2 Sep 2004 01:52:35 -0000
***************
*** 130,136 ****
(eq_attr "cpu" "power4"))
"lsq_power4")
! (define_insn_reservation "power4-store" 1
(and (eq_attr "type" "store")
(eq_attr "cpu" "power4"))
"(du1_power4,lsu1_power4,iu1_power4)\
--- 130,136 ----
(eq_attr "cpu" "power4"))
"lsq_power4")
! (define_insn_reservation "power4-store" 12
(and (eq_attr "type" "store")
(eq_attr "cpu" "power4"))
"(du1_power4,lsu1_power4,iu1_power4)\
***************
*** 138,144 ****
|(du3_power4,lsu2_power4,nothing,iu2_power4)\
|(du4_power4,lsu1_power4,nothing,iu1_power4)")
! (define_insn_reservation "power4-store-update" 1
(and (eq_attr "type" "store_u")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
--- 138,144 ----
|(du3_power4,lsu2_power4,nothing,iu2_power4)\
|(du4_power4,lsu1_power4,nothing,iu1_power4)")
! (define_insn_reservation "power4-store-update" 12
(and (eq_attr "type" "store_u")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
***************
*** 146,158 ****
|(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
|(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")
! (define_insn_reservation "power4-store-update-indexed" 1
(and (eq_attr "type" "store_ux")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
! (define_insn_reservation "power4-fpstore" 1
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power4"))
"(du1_power4,lsu1_power4,fpu1_power4)\
--- 146,158 ----
|(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
|(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")
! (define_insn_reservation "power4-store-update-indexed" 12
(and (eq_attr "type" "store_ux")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
! (define_insn_reservation "power4-fpstore" 12
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power4"))
"(du1_power4,lsu1_power4,fpu1_power4)\
***************
*** 160,166 ****
|(du3_power4,lsu2_power4,nothing,fpu2_power4)\
|(du4_power4,lsu1_power4,nothing,fpu1_power4)")
! (define_insn_reservation "power4-fpstore-update" 1
(and (eq_attr "type" "fpstore_u,fpstore_ux")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
--- 160,166 ----
|(du3_power4,lsu2_power4,nothing,fpu2_power4)\
|(du4_power4,lsu1_power4,nothing,fpu1_power4)")
! (define_insn_reservation "power4-fpstore-update" 12
(and (eq_attr "type" "fpstore_u,fpstore_ux")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
***************
*** 168,174 ****
|(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")
; |(du3_power4+du4_power4,nothing,lsu2_power4+iu1_power4,fpu2_power4)")
! (define_insn_reservation "power4-vecstore" 1
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power4"))
"(du1_power4,lsu1_power4,vec_power4)\
--- 168,174 ----
|(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")
; |(du3_power4+du4_power4,nothing,lsu2_power4+iu1_power4,fpu2_power4)")
! (define_insn_reservation "power4-vecstore" 12
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power4"))
"(du1_power4,lsu1_power4,vec_power4)\
Index: power5.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/power5.md,v
retrieving revision 1.1
diff -c -p -r1.1 power5.md
*** power5.md 25 Mar 2004 17:43:23 -0000 1.1
--- power5.md 2 Sep 2004 01:52:35 -0000
***************
*** 103,109 ****
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5")
! (define_insn_reservation "power5-store" 1
(and (eq_attr "type" "store")
(eq_attr "cpu" "power5"))
"(du1_power5,lsu1_power5,iu1_power5)\
--- 103,109 ----
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5")
! (define_insn_reservation "power5-store" 12
(and (eq_attr "type" "store")
(eq_attr "cpu" "power5"))
"(du1_power5,lsu1_power5,iu1_power5)\
***************
*** 111,128 ****
|(du3_power5,lsu2_power5,nothing,iu2_power5)\
|(du4_power5,lsu1_power5,nothing,iu1_power5)")
! (define_insn_reservation "power5-store-update" 1
(and (eq_attr "type" "store_u")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
! (define_insn_reservation "power5-store-update-indexed" 1
(and (eq_attr "type" "store_ux")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
! (define_insn_reservation "power5-fpstore" 1
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power5"))
"(du1_power5,lsu1_power5,fpu1_power5)\
--- 111,128 ----
|(du3_power5,lsu2_power5,nothing,iu2_power5)\
|(du4_power5,lsu1_power5,nothing,iu1_power5)")
! (define_insn_reservation "power5-store-update" 12
(and (eq_attr "type" "store_u")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
! (define_insn_reservation "power5-store-update-indexed" 12
(and (eq_attr "type" "store_ux")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
! (define_insn_reservation "power5-fpstore" 12
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power5"))
"(du1_power5,lsu1_power5,fpu1_power5)\
***************
*** 130,136 ****
|(du3_power5,lsu2_power5,nothing,fpu2_power5)\
|(du4_power5,lsu1_power5,nothing,fpu1_power5)")
! (define_insn_reservation "power5-fpstore-update" 1
(and (eq_attr "type" "fpstore_u,fpstore_ux")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
--- 130,136 ----
|(du3_power5,lsu2_power5,nothing,fpu2_power5)\
|(du4_power5,lsu1_power5,nothing,fpu1_power5)")
! (define_insn_reservation "power5-fpstore-update" 12
(and (eq_attr "type" "fpstore_u,fpstore_ux")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")