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[PATCH] new altivec tests to verify statements in manual
- From: Janis Johnson <janis187 at us dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 13 Aug 2004 10:18:40 -0700
- Subject: [PATCH] new altivec tests to verify statements in manual
Yesterday I submitted a documentation patch to add a couple of statements
about additional differences in GCC's AltiVec support from the Motorola
AltiVec PIM. These tests verify those statements. OK for mainline?
2004-08-13 Janis Johnson <janis187@us.ibm.com>
* gcc.dg/altivec-17.c: New test.
* gcc.dg/altivec-18.c: New test.
--- /dev/null 2004-06-24 11:06:20.000000000 -0700
+++ testsuite/gcc.dg/altivec-17.c 2004-08-13 10:07:31.000000000 -0700
@@ -0,0 +1,11 @@
+/* Verify a statement in the GCC Manual that GCC allows the use of a
+ typedef name as a vector type specifier. */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+
+typedef unsigned int ui;
+typedef signed char sc;
+__vector ui vui;
+__vector sc vsc;
--- /dev/null 2004-06-24 11:06:20.000000000 -0700
+++ testsuite/gcc.dg/altivec-18.c 2004-08-13 10:07:31.000000000 -0700
@@ -0,0 +1,23 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+/* { dg-final { scan-assembler "vcmpgtub" } } */
+/* { dg-final { scan-assembler "vcmpgtsh" } } */
+/* { dg-final { scan-assembler "vcmpgtsw" } } */
+
+/* Verify a statement in the GCC Manual that vector type specifiers can
+ omit "signed" or "unsigned", with the default being "signed" for int
+ and short, and "unsigned" for char. */
+
+#include <altivec.h>
+
+extern vector char vc1, vc2;
+extern vector short vs1, vs2;
+extern vector int vi1, vi2;
+
+int signedness (void)
+{
+ return vec_all_le (vc1, vc2)
+ && vec_all_le (vs1, vs2)
+ && vec_all_le (vi1, vi2);
+}