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Re: cr logical instruction for powerpc target
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: Geoff Keating <geoffk at geoffk dot org>, Gabriel Paubert <paubert at iram dot es>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Wed, 11 Aug 2004 15:19:53 -0400
- Subject: Re: cr logical instruction for powerpc target
- References: <4118BD16.5040109@thalescomputers.fr> <200408101423.i7AEN6D27398@makai.watson.ibm.com> <20040811103459.GA15723@iram.es> <200408111445.i7BEjpD33858@makai.watson.ibm.com> <C05050DF-EBC6-11D8-A2DC-000A95B1F520@geoffk.org>
>>>>> Geoff Keating writes:
>> I think it can be changed to "8", but maybe Geoff had a reason for
>> leaving it "12".
Geoff> No, it should be 8.
I changed all of the patterns appropriately.
David
* config/rs6000/rs6000.md (mfcr rlwinm patterns): Set length to 8.
(mfcr rlwinm rlwinm patterns): Set length to 12.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.316
diff -c -p -r1.316 rs6000.md
*** rs6000.md 11 Aug 2004 02:40:43 -0000 1.316
--- rs6000.md 11 Aug 2004 18:59:30 -0000
***************
*** 11390,11396 ****
(const_string "mfcrf")
]
(const_string "mfcr")))
! (set_attr "length" "12")])
;; Same as above, but get the GT bit.
(define_insn "move_from_CR_eq_bit"
--- 11390,11396 ----
(const_string "mfcrf")
]
(const_string "mfcr")))
! (set_attr "length" "8")])
;; Same as above, but get the GT bit.
(define_insn "move_from_CR_eq_bit"
***************
*** 11399,11405 ****
"TARGET_E500"
"mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "12")])
;; Same as above, but get the OV/ORDERED bit.
(define_insn "move_from_CR_ov_bit"
--- 11399,11405 ----
"TARGET_E500"
"mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "8")])
;; Same as above, but get the OV/ORDERED bit.
(define_insn "move_from_CR_ov_bit"
***************
*** 11408,11414 ****
"TARGET_ISEL"
"mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--- 11408,11414 ----
"TARGET_ISEL"
"mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
***************
*** 11422,11428 ****
(const_string "mfcrf")
]
(const_string "mfcr")))
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
--- 11422,11428 ----
(const_string "mfcrf")
]
(const_string "mfcr")))
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
***************
*** 11437,11443 ****
mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
#"
[(set_attr "type" "delayed_compare")
! (set_attr "length" "12,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
--- 11437,11443 ----
mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
#"
[(set_attr "type" "delayed_compare")
! (set_attr "length" "8,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
***************
*** 11483,11489 ****
(const_string "mfcrf")
]
(const_string "mfcr")))
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
--- 11483,11489 ----
(const_string "mfcrf")
]
(const_string "mfcr")))
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
***************
*** 11518,11524 ****
return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
}"
[(set_attr "type" "delayed_compare")
! (set_attr "length" "12,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
--- 11518,11524 ----
return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
}"
[(set_attr "type" "delayed_compare")
! (set_attr "length" "8,16")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
***************
*** 11555,11561 ****
"REGNO (operands[2]) != REGNO (operands[5])"
"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "20")])
(define_peephole
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--- 11555,11561 ----
"REGNO (operands[2]) != REGNO (operands[5])"
"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "12")])
(define_peephole
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
***************
*** 11569,11575 ****
"TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "20")])
;; There are some scc insns that can be done directly, without a compare.
;; These are faster because they don't involve the communications between
--- 11569,11575 ----
"TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
"mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "type" "mfcr")
! (set_attr "length" "12")])
;; There are some scc insns that can be done directly, without a compare.
;; These are faster because they don't involve the communications between