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[committed] target/16144: Calling __divdf3 in hard-float code
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 25 Jun 2004 08:01:56 +0100
- Subject: [committed] target/16144: Calling __divdf3 in hard-float code
PR target/16144 is about hard-float MIPS code using __divdf3 to
implement divisions of the form 1.0/x. This is because the division
expanders were "FAIL"ing if they couldn't implement the division using
a reciprocal instruction. They should just force the constant into a
register instead.
Tested on mips64-linux-gnu, applied to HEAD.
Richard
PR target/16144
* config/mips/mips.md (divsf, divdf): Don't FAIL if the first operand
is 1.0; force it into a register instead.
testsuite/
* gcc.dg/torture/mips-div-1.c: New test.
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.211.4.6
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.211.4.6 mips.md
--- config/mips/mips.md 29 Apr 2004 19:55:28 -0000 1.211.4.6
+++ config/mips/mips.md 24 Jun 2004 17:26:13 -0000
@@ -2374,7 +2374,7 @@ (define_expand "divdf3"
{
if (const_float_1_operand (operands[1], DFmode))
if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
- FAIL;
+ operands[1] = force_reg (DFmode, operands[1]);
})
;; This pattern works around the early SB-1 rev2 core "F1" erratum:
@@ -2424,7 +2424,7 @@ (define_expand "divsf3"
{
if (const_float_1_operand (operands[1], SFmode))
if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
- FAIL;
+ operands[1] = force_reg (SFmode, operands[1]);
})
;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
--- /dev/null Fri Apr 23 00:21:55 2004
+++ testsuite/gcc.dg/torture/mips-div-1.c Thu Jun 24 18:07:22 2004
@@ -0,0 +1,9 @@
+/* Check that hard-float MIPS code doesn't use library calls for 1.0/x. */
+/* { dg-options "-fno-delayed-branch" } */
+/* { dg-do compile { target mips*-*-* } } */
+
+float f1 (float x) { return 1.0f / x; }
+double f2 (double x) { return 1.0 / x; }
+
+/* { dg-final { scan-assembler-not {lwc1.*__divsf3} } } */
+/* { dg-final { scan-assembler-not {ldc1.*__divdf3} } } */