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[patch 3.3/3.4] Fix for PR 15202
- From: "John David Anglin" <dave at hiauly1 dot hia dot nrc dot ca>
- To: gcc-patches at gcc dot gnu dot org
- Cc: mark at codesourcery dot com, gdr at integrable-solutions dot net
- Date: Sun, 16 May 2004 22:32:09 -0400 (EDT)
- Subject: [patch 3.3/3.4] Fix for PR 15202
The following patch fixes PR 15202. The fix isn't a for a regression
because as far as I know we never supported copying the SAR register
(shift amount register) back to a general register. I believe this was
omitted on purpose as the SAR register is 5 or 6 bits when generating
PA 1.x and 2.0 code, respectively. Thus, we don't want to copy to/from
the SAR register in general. However, the testcase submitted with
the PR shows that we need to be able to copy back from the SAR register
under rare circumstances. Copying from the SAR register is inhibited
by giving it a high cost.
The enclosed patch changes the machine definition to support this copy.
The copy is disparaged so that it should only occur if reloads aren't
required.
This seems a bit of a hack but there isn't a good way to handle a
5/6 bit register in GCC. I think hiding the register until after
reload would produce worse code. Since we didn't miss being able
to copy from the SAR register until PR 15202, I think adding this
capability is safe. In any event, the fix only affects the PA.
I am currently testing the enclosed patch on hppa64-hp-hpux11.00.
It has successfully completed testing on hppa2.0w-hp-hpux11.00.
I am testing a similar patch for the 3.3 branch on hppa-unknown-linux-gnu.
A similar fix has been on the main for a week or so.
Is this ok for 3.3 and 3.4?
Dave
--
J. David Anglin dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada (613) 990-0752 (FAX: 952-6602)
2004-05-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR target/15202
* pa.md (movdi, movsi, movhi, movqi): Support move from shift amount
register to general register for DI, SI, HI and QI modes. Remove
move to shift amount register in DF mode.
Index: config/pa/pa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.md,v
retrieving revision 1.138.4.5
diff -u -3 -p -r1.138.4.5 pa.md
--- config/pa/pa.md 6 Apr 2004 09:03:53 -0000 1.138.4.5
+++ config/pa/pa.md 16 May 2004 18:02:49 -0000
@@ -2264,9 +2264,9 @@
(define_insn ""
[(set (match_operand:SI 0 "move_dest_operand"
- "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
+ "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
(match_operand:SI 1 "move_src_operand"
- "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
+ "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
"(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))
&& !TARGET_SOFT_FLOAT"
@@ -2279,12 +2279,13 @@
ldw%M1 %1,%0
stw%M0 %r1,%0
mtsar %r1
+ {mfctl|mfctl,w} %%sar,%0
fcpy,sgl %f1,%0
fldw%F1 %1,%0
fstw%F0 %1,%0"
- [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
+ [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
(define_insn ""
[(set (match_operand:SI 0 "indexed_memory_operand" "=R")
@@ -2433,9 +2434,9 @@
(define_insn ""
[(set (match_operand:SI 0 "move_dest_operand"
- "=r,r,r,r,r,r,Q,!*q")
+ "=r,r,r,r,r,r,Q,!*q,!r")
(match_operand:SI 1 "move_src_operand"
- "A,r,J,N,K,RQ,rM,!rM"))]
+ "A,r,J,N,K,RQ,rM,!rM,!*q"))]
"(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))
&& TARGET_SOFT_FLOAT"
@@ -2447,10 +2448,11 @@
{zdepi|depwi,z} %Z1,%0
ldw%M1 %1,%0
stw%M0 %r1,%0
- mtsar %r1"
- [(set_attr "type" "load,move,move,move,move,load,store,move")
+ mtsar %r1
+ {mfctl|mfctl,w} %%sar,%0"
+ [(set_attr "type" "load,move,move,move,move,load,store,move,move")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4")])
;; Load or store with base-register modification.
(define_insn ""
@@ -2867,9 +2869,9 @@
(define_insn ""
[(set (match_operand:HI 0 "move_dest_operand"
- "=r,r,r,r,r,Q,!*q,!*f")
+ "=r,r,r,r,r,Q,!*q,!r,!*f")
(match_operand:HI 1 "move_src_operand"
- "r,J,N,K,RQ,rM,!rM,!*fM"))]
+ "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
"register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode)"
"@
@@ -2880,10 +2882,11 @@
ldh%M1 %1,%0
sth%M0 %r1,%0
mtsar %r1
+ {mfctl|mfctl,w} %sar,%0
fcpy,sgl %f1,%0"
- [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
+ [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2991,9 +2994,9 @@
(define_insn ""
[(set (match_operand:QI 0 "move_dest_operand"
- "=r,r,r,r,r,Q,!*q,!*f")
+ "=r,r,r,r,r,Q,!*q,!r,!*f")
(match_operand:QI 1 "move_src_operand"
- "r,J,N,K,RQ,rM,!rM,!*fM"))]
+ "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
"register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode)"
"@
@@ -3004,10 +3007,11 @@
ldb%M1 %1,%0
stb%M0 %r1,%0
mtsar %r1
+ {mfctl|mfctl,w} %%sar,%0
fcpy,sgl %f1,%0"
- [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
+ [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4")])
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -3958,9 +3962,9 @@
(define_insn ""
[(set (match_operand:DF 0 "move_dest_operand"
- "=!*r,*r,*r,*r,*r,Q,!*q,f,f,T")
+ "=!*r,*r,*r,*r,*r,Q,f,f,T")
(match_operand:DF 1 "move_src_operand"
- "!*r,J,N,K,RQ,*rM,!*rM,fM,RT,f"))]
+ "!*r,J,N,K,RQ,*rM,fM,RT,f"))]
"(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))
&& !TARGET_SOFT_FLOAT && TARGET_64BIT"
@@ -3971,13 +3975,12 @@
depdi,z %z1,%0
ldd%M1 %1,%0
std%M0 %r1,%0
- mtsar %r1
fcpy,dbl %f1,%0
fldd%F1 %1,%0
fstd%F0 %1,%0"
- [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
+ [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4")])
(define_expand "movdi"
@@ -4082,9 +4085,9 @@
(define_insn ""
[(set (match_operand:DI 0 "move_dest_operand"
- "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
+ "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
(match_operand:DI 1 "move_src_operand"
- "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
+ "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
"(register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))
&& !TARGET_SOFT_FLOAT && TARGET_64BIT"
@@ -4097,12 +4100,13 @@
ldd%M1 %1,%0
std%M0 %r1,%0
mtsar %r1
+ {mfctl|mfctl,w} %%sar,%0
fcpy,dbl %f1,%0
fldd%F1 %1,%0
fstd%F0 %1,%0"
- [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
+ [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
(set_attr "pa_combine_type" "addmove")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
(define_insn ""
[(set (match_operand:DI 0 "indexed_memory_operand" "=R")