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Re: [committed] Canonicalise VR5500 branch-likely check
- From: cgd at broadcom dot com
- To: rsandifo at redhat dot com
- Cc: gcc-patches at gcc dot gnu dot org
- Date: 13 May 2004 11:38:27 -0700
- Subject: Re: [committed] Canonicalise VR5500 branch-likely check
- References: <87n04kl1gz.fsf@redhat.com><mailpost.1083942501.15698@news-sj1-1>
At Fri, 7 May 2004 15:08:21 +0000 (UTC), "Richard Sandiford" wrote:
> ISA_HAS_CONDMOVE suffers from a similar problem, but there's no
> GENERATE_CONDMOVE yet, so I'm afraid that's still on the to-do list.
speaking of which... i actually wanted to mess around with the
effects of using/not using condmove generation myself, so i coded the
following up.
Run through the testsuite (c,c++ for sb1-elf), and sanity checked, but
not beaten extensively. (well, OK, i have run SPEC CPU95 through it
repeatedly on mips64-linux, too, but that's still not a heavy
beating. 8-)
Do with it what you will. Note that it chews one of the last few
remaining unused target flags, and also gets rid of the long-present
and ever-unused ISA_HAS_INT_CONDMOVE define.
Also note that if somebody wants to commit this, the new option should
be documented. I didn't bother since i implemented it for
experimentation only. (I almost didn't bother to write a ChangeLog
entry. 8-)
chris
--
2004-05-13 Chris Demetriou <cgd@broadcom.com>
* config/mips/mips.c (override_options): Handle setup of MASK_CONDMOVE.
* config/mips/mips.h (MASK_CONDMOVE, TARGET_CONDMOVE): Define.
(GENERATE_CONDMOVE): Define.
(TARGET_SWITCHES): Add cases for -mcondmove and -mno-condmove.
(ISA_HAS_INT_CONDMOVE): Remove.
* config/mips/mips.md: Replace all uses of ISA_HAS_CONDMOVE and
ISA_HAS_INT_CONDMOVE with GENERATE_CONDMOVE.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.414
diff -u -p -r1.414 mips.c
--- config/mips/mips.c 7 May 2004 15:09:23 -0000 1.414
+++ config/mips/mips.c 13 May 2004 18:36:38 -0000
@@ -4767,6 +4767,22 @@ override_options (void)
if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
+ if ((target_flags_explicit & MASK_CONDMOVE) == 0)
+ {
+ /* If neither -mcondmove nor -mno-condmove was given on the command
+ line, set MASK_CONDMOVE based on the target architecture.
+
+ By default, we enable use of Branch Likely instructions on all
+ architectures which support them except when tuning for
+ architectures where their use tends to hurt performance. */
+ if (ISA_HAS_CONDMOVE)
+ target_flags |= MASK_CONDMOVE;
+ else
+ target_flags &= ~MASK_CONDMOVE;
+ }
+ if (TARGET_CONDMOVE && !ISA_HAS_CONDMOVE)
+ warning ("generation of conditional move instructions enabled, but not supported by architecture");
+
/* The effect of -mabicalls isn't defined for the EABI. */
if (mips_abi == ABI_EABI && TARGET_ABICALLS)
{
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.341
diff -u -p -r1.341 mips.h
--- config/mips/mips.h 7 May 2004 15:06:15 -0000 1.341
+++ config/mips/mips.h 13 May 2004 18:36:39 -0000
@@ -173,6 +173,8 @@ extern const struct mips_cpu_info *mips_
#define MASK_FIX_VR4120 0x04000000 /* Work around VR4120 errata. */
#define MASK_VR4130_ALIGN 0x08000000 /* Perform VR4130 alignment opts. */
#define MASK_FP_EXCEPTIONS 0x10000000 /* FP exceptions are enabled. */
+#define MASK_CONDMOVE 0x20000000 /* Generate Condition Move
+ instructions. */
/* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */
@@ -257,6 +259,8 @@ extern const struct mips_cpu_info *mips_
#define TARGET_FP_EXCEPTIONS (target_flags & MASK_FP_EXCEPTIONS)
+#define TARGET_CONDMOVE (target_flags & MASK_CONDMOVE)
+
/* True if we should use NewABI-style relocation operators for
symbolic addresses. This is never true for mips16 code,
which has its own conventions. */
@@ -656,6 +660,10 @@ extern const struct mips_cpu_info *mips_
N_("Use Branch Likely instructions, overriding default for arch")}, \
{ "no-branch-likely", -MASK_BRANCHLIKELY, \
N_("Don't use Branch Likely instructions, overriding default for arch")}, \
+ { "condmove", MASK_CONDMOVE, \
+ N_("Use conditional move instructions, overriding default for arch")}, \
+ { "no-condmove", -MASK_CONDMOVE, \
+ N_("Don't use conditional move instructions, overriding default for arch")}, \
{"explicit-relocs", MASK_EXPLICIT_RELOCS, \
N_("Use NewABI-style %reloc() assembly operators")}, \
{"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
@@ -868,8 +876,8 @@ extern const struct mips_cpu_info *mips_
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
-/* ISA has just the integer condition move instructions (movn,movz) */
-#define ISA_HAS_INT_CONDMOVE 0
+#define GENERATE_CONDMOVE (TARGET_CONDMOVE \
+ && !TARGET_MIPS16)
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.243
diff -u -p -r1.243 mips.md
--- config/mips/mips.md 10 May 2004 18:35:43 -0000 1.243
+++ config/mips/mips.md 13 May 2004 18:36:40 -0000
@@ -8834,7 +8834,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ "GENERATE_CONDMOVE"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
@@ -8849,7 +8849,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ "GENERATE_CONDMOVE"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
@@ -8865,7 +8865,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
+ "GENERATE_CONDMOVE"
"@
mov%T3\t%0,%z1,%4
mov%t3\t%0,%z2,%4"
@@ -8880,7 +8880,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
+ "GENERATE_CONDMOVE && TARGET_64BIT"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
@@ -8895,7 +8895,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
+ "GENERATE_CONDMOVE && TARGET_64BIT"
"@
mov%B4\t%0,%z2,%1
mov%b4\t%0,%z3,%1"
@@ -8911,7 +8911,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:DI 1 "reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
"@
mov%T3\t%0,%z1,%4
mov%t3\t%0,%z2,%4"
@@ -8926,7 +8926,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\t%0,%2,%1
mov%b4.s\t%0,%3,%1"
@@ -8941,7 +8941,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%B4.s\t%0,%2,%1
mov%b4.s\t%0,%3,%1"
@@ -8957,7 +8957,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT"
"@
mov%T3.s\t%0,%1,%4
mov%t3.s\t%0,%2,%4"
@@ -8972,7 +8972,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\t%0,%2,%1
mov%b4.d\t%0,%3,%1"
@@ -8987,7 +8987,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\t%0,%2,%1
mov%b4.d\t%0,%3,%1"
@@ -9003,7 +9003,7 @@ srl\t%M0,%M1,%2\n\
(const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%T3.d\t%0,%1,%4
mov%t3.d\t%0,%2,%4"
@@ -9018,7 +9018,7 @@ srl\t%M0,%M1,%2\n\
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand")
(match_operand:SI 3 "reg_or_0_operand")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ "GENERATE_CONDMOVE"
{
gen_conditional_move (operands);
DONE;
@@ -9030,7 +9030,7 @@ srl\t%M0,%M1,%2\n\
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "reg_or_0_operand")
(match_operand:DI 3 "reg_or_0_operand")))]
- "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
+ "GENERATE_CONDMOVE && TARGET_64BIT"
{
gen_conditional_move (operands);
DONE;
@@ -9042,7 +9042,7 @@ srl\t%M0,%M1,%2\n\
(if_then_else:SF (match_dup 5)
(match_operand:SF 2 "register_operand")
(match_operand:SF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT"
{
gen_conditional_move (operands);
DONE;
@@ -9054,7 +9054,7 @@ srl\t%M0,%M1,%2\n\
(if_then_else:DF (match_dup 5)
(match_operand:DF 2 "register_operand")
(match_operand:DF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "GENERATE_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
gen_conditional_move (operands);
DONE;