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RFA: patch - tuning gcc for Intel Nocona (64 bit).
- From: Vladimir Makarov <vmakarov at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 01 Apr 2004 15:00:09 -0500
- Subject: RFA: patch - tuning gcc for Intel Nocona (64 bit).
The following patch tunes gcc to Nocona Xeon. The SPEC2000
results for mainline gcc for 2.8Ghz Nocona Xeon in 64-bit mode (using
x86_64 insns) are given below.
SPECFP2000 is 28% faster with the tuning. SPECInt2000 is 0.6%
faster. The code size (text segment) is also usually smaller.
IMHO, there are still other possibilities to tune the code for
Nocona. These ones are only the simplest ones.
I see one problem what tunning will be the default for x86_64. I
don't think that e.g. Linux distributions will have different code for
Intel Nocona and AMD Opteron.
Vlad
Base: -O2
Peak: -O2 -mtune=nocona
SPECInt2000 base peak
=============================================================
164.gzip 1400 186 753* 1400 183 764*
175.vpr 1400 218 641* 1400 215 650*
176.gcc 1100 102 1081* 1100 98.4 1118*
181.mcf 1800 362 497* 1800 364 494*
186.crafty 1000 85.7 1167* 1000 87.0 1150*
197.parser 1800 273 659* 1800 275 654*
252.eon X X
253.perlbmk 1800 153 1176* 1800 152 1186*
254.gap 1100 95.8 1148* 1100 95.4 1153*
255.vortex 1900 154 1230* 1900 157 1214*
256.bzip2 1500 180 832* 1500 176 853*
300.twolf 3000 390 770* 3000 388 774*
Est. SPECint_base2000 868
Est. SPECint2000 873
----------------CINT2000-----------------
-4.003% 101249 97196 197.parser
-1.721% 137763 135392 175.vpr
-3.579% 573087 552578 255.vortex
-1.506% 30800 30336 256.bzip2
-3.582% 550705 530980 253.perlbmk
-4.354% 523548 500752 252.eon
-1.416% 185083 182462 300.twolf
-3.727% 471741 454160 254.gap
-2.783% 1.41256e+06 1.37325e+06 176.gcc
-0.065% 166675 166566 186.crafty
-2.033% 37627 36862 164.gzip
-1.723% 12074 11866 181.mcf
SPECFp2000 base peak
======================================================================
168.wupwise 1600 171 936 * 1600 132 1216 *
171.swim 3100 270 1150 * 3100 210 1477 *
172.mgrid 1800 492 366 * 1800 303 595 *
173.applu 2100 306 686 * 2100 231 908 *
177.mesa 1400 122 1152 * 1400 120 1167 *
178.galgel X X
179.art 2600 334 779 * 2600 326 798 *
183.equake 1300 110 1179 * 1300 93.4 1392 *
187.facerec X X
188.ammp X X
189.lucas X X
191.fma3d X X
200.sixtrack 1100 435 253 * 1100 242 455 *
301.apsi 2600 429 606 * 2600 369 705 *
Est. SPECfp_base2000 706
Est. SPECfp2000 904
----------------CFP2000-----------------
5.005% 8792 9232 171.swim
-1.158% 19340 19116 183.equake
-0.251% 12769 12737 172.mgrid
-1.619% 15316 15068 179.art
-0.527% 28821 28669 168.wupwise
-4.078% 495562 475354 177.mesa
-0.072% 865962 865338 200.sixtrack
-0.483% 125935 125327 301.apsi
4.811% 46231 48455 173.applu
2004-04-01 Vladimir Makarov <vmakarov@redhat.com>
* config/i386/i386.h (TARGET_NOCONA): New macro.
(TARGET_CPU_CPP_BUILTINS): Add code for Nocona.
(processor_type): Add PROCESSOR_NOCONA.
* config/i386/i386.c (nocona_cost): New variable.
(m_NOCONA): New macro.
(x86_push_memory, x86_movx, x86_cmove, x86_deep_branch,
x86_branch_hints, x86_use_sahf, x86_single_stringop,
x86_sub_esp_4, x86_sub_esp_8, x86_add_esp_4, x86_add_esp_8,
x86_integer_DFmode_moves, x86_partial_reg_dependency,
x86_memory_mismatch_stall, x86_accumulate_outgoing_args,
x86_decompose_lea, x86_arch_always_fancy_math_387,
x86_sse_partial_reg_dependency, x86_sse_load0_by_pxor,
x86_ext_80387_constants, x86_four_jump_limit):
(override_options): Add nocona_cost to processor_target_table.
Set up PROCESSOR_NOCONA for Nocona entry in processor_alias_table.
(incdec_operand): Prevent inc/dec generation for Nocona too.
(ix86_issue_rate): Add PROCESSOR_NOCONA.
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.660
diff -c -d -p -r1.660 i386.c
*** config/i386/i386.c 16 Mar 2004 23:29:21 -0000 1.660
--- config/i386/i386.c 1 Apr 2004 19:26:41 -0000
*************** struct processor_costs pentium4_cost = {
*** 457,462 ****
--- 457,506 ----
43, /* cost of FSQRT instruction. */
};
+ static const
+ struct processor_costs nocona_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* variable shift costs */
+ 1, /* constant shift costs */
+ {10, 10, 10, 10, 10}, /* cost of starting a multiply */
+ 0, /* cost of multiply per each bit set */
+ {66, 66, 66, 66, 66}, /* cost of a divide/mod */
+ 1, /* cost of movsx */
+ 1, /* cost of movzx */
+ 16, /* "large" insn */
+ 9, /* MOVE_RATIO */
+ 4, /* cost for loading QImode using movzbl */
+ {4, 4, 4}, /* cost of loading integer registers
+ in QImode, HImode and SImode.
+ Relative to reg-reg move (2). */
+ {4, 4, 4}, /* cost of storing integer registers */
+ 3, /* cost of reg,reg fld/fst */
+ {12, 12, 12}, /* cost of loading fp registers
+ in SFmode, DFmode and XFmode */
+ {4, 4, 4}, /* cost of loading integer registers */
+ 6, /* cost of moving MMX register */
+ {12, 12}, /* cost of loading MMX registers
+ in SImode and DImode */
+ {12, 12}, /* cost of storing MMX registers
+ in SImode and DImode */
+ 6, /* cost of moving SSE register */
+ {12, 12, 12}, /* cost of loading SSE registers
+ in SImode, DImode and TImode */
+ {12, 12, 12}, /* cost of storing SSE registers
+ in SImode, DImode and TImode */
+ 8, /* MMX or SSE register to integer */
+ 128, /* size of prefetch block */
+ 8, /* number of parallel prefetches */
+ 1, /* Branch cost */
+ 6, /* cost of FADD and FSUB insns. */
+ 8, /* cost of FMUL instruction. */
+ 40, /* cost of FDIV instruction. */
+ 3, /* cost of FABS instruction. */
+ 3, /* cost of FCHS instruction. */
+ 44, /* cost of FSQRT instruction. */
+ };
+
const struct processor_costs *ix86_cost = &pentium_cost;
/* Processor feature/optimization bitmasks. */
*************** const struct processor_costs *ix86_cost
*** 469,487 ****
#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
#define m_K8 (1<<PROCESSOR_K8)
#define m_ATHLON_K8 (m_K8 | m_ATHLON)
const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8;
! const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4;
const int x86_zero_extend_with_and = m_486 | m_PENT;
! const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 /* m_386 | m_K6 */;
const int x86_double_with_add = ~m_386;
const int x86_use_bit_test = m_386;
const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6;
! const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4;
const int x86_3dnow_a = m_ATHLON_K8;
! const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4;
! const int x86_branch_hints = m_PENT4;
! const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4;
const int x86_partial_reg_stall = m_PPRO;
const int x86_use_loop = m_K6;
const int x86_use_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT);
--- 513,532 ----
#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
#define m_K8 (1<<PROCESSOR_K8)
#define m_ATHLON_K8 (m_K8 | m_ATHLON)
+ #define m_NOCONA (1<<PROCESSOR_NOCONA)
const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8;
! const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_zero_extend_with_and = m_486 | m_PENT;
! const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA /* m_386 | m_K6 */;
const int x86_double_with_add = ~m_386;
const int x86_use_bit_test = m_386;
const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6;
! const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_3dnow_a = m_ATHLON_K8;
! const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
! const int x86_branch_hints = m_PENT4 | m_NOCONA;
! const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA;
const int x86_partial_reg_stall = m_PPRO;
const int x86_use_loop = m_K6;
const int x86_use_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT);
*************** const int x86_read_modify = ~(m_PENT | m
*** 492,516 ****
const int x86_split_long_moves = m_PPRO;
const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8;
const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
! const int x86_single_stringop = m_386 | m_PENT4;
const int x86_qimode_math = ~(0);
const int x86_promote_qi_regs = 0;
const int x86_himode_math = ~(m_PPRO);
const int x86_promote_hi_regs = m_PPRO;
! const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4;
! const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4;
! const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4;
! const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4;
! const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_PPRO);
! const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4;
! const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4;
! const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_PPRO;
const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO;
const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO;
! const int x86_decompose_lea = m_PENT4;
const int x86_shift1 = ~m_486;
! const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4;
! const int x86_sse_partial_reg_dependency = m_PENT4 | m_PPRO;
/* Set for machines where the type and dependencies are resolved on SSE register
parts instead of whole registers, so we may maintain just lower part of
scalar values in proper format leaving the upper part undefined. */
--- 537,561 ----
const int x86_split_long_moves = m_PPRO;
const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8;
const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
! const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
const int x86_qimode_math = ~(0);
const int x86_promote_qi_regs = 0;
const int x86_himode_math = ~(m_PPRO);
const int x86_promote_hi_regs = m_PPRO;
! const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA;
! const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA;
! const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA;
! const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA;
! const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO);
! const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
! const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
! const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO;
const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO;
const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO;
! const int x86_decompose_lea = m_PENT4 | m_NOCONA;
const int x86_shift1 = ~m_486;
! const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
! const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO;
/* Set for machines where the type and dependencies are resolved on SSE register
parts instead of whole registers, so we may maintain just lower part of
scalar values in proper format leaving the upper part undefined. */
*************** const int x86_sse_partial_regs = m_ATHLO
*** 519,532 ****
need for extra instructions beforehand */
const int x86_sse_partial_regs_for_cvtsd2ss = 0;
const int x86_sse_typeless_stores = m_ATHLON_K8;
! const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4;
const int x86_use_ffreep = m_ATHLON_K8;
const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
const int x86_inter_unit_moves = ~(m_ATHLON_K8);
! const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_PPRO;
/* Some CPU cores are not able to predict more than 4 branch instructions in
the 16 byte window. */
! const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4;
/* In case the average insn count for single function invocation is
lower than this constant, emit fast (but longer) prologue and
--- 564,577 ----
need for extra instructions beforehand */
const int x86_sse_partial_regs_for_cvtsd2ss = 0;
const int x86_sse_typeless_stores = m_ATHLON_K8;
! const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
const int x86_use_ffreep = m_ATHLON_K8;
const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
const int x86_inter_unit_moves = ~(m_ATHLON_K8);
! const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO;
/* Some CPU cores are not able to predict more than 4 branch instructions in
the 16 byte window. */
! const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
/* In case the average insn count for single function invocation is
lower than this constant, emit fast (but longer) prologue and
*************** static void init_ext_80387_constants (vo
*** 1025,1030 ****
--- 1070,1076 ----
#define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
struct gcc_target targetm = TARGET_INITIALIZER;
+
/* The svr4 ABI for the i386 says that records and unions are returned
in memory. */
*************** override_options (void)
*** 1068,1074 ****
{&k6_cost, 0, 0, 32, 7, 32, 7, 32},
{&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
{&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
! {&k8_cost, 0, 0, 16, 7, 16, 7, 16}
};
static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
--- 1114,1121 ----
{&k6_cost, 0, 0, 32, 7, 32, 7, 32},
{&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
{&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
! {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
! {&nocona_cost, 0, 0, 0, 0, 0, 0, 0}
};
static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
*************** override_options (void)
*** 1109,1118 ****
| PTA_MMX | PTA_PREFETCH_SSE},
{"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
| PTA_MMX | PTA_PREFETCH_SSE},
! {"prescott", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_MMX | PTA_PREFETCH_SSE},
- {"nocona", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
- | PTA_MMX | PTA_PREFETCH_SSE},
{"k6", PROCESSOR_K6, PTA_MMX},
{"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
{"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
--- 1156,1165 ----
| PTA_MMX | PTA_PREFETCH_SSE},
{"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
| PTA_MMX | PTA_PREFETCH_SSE},
! {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
! | PTA_MMX | PTA_PREFETCH_SSE},
! {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
| PTA_MMX | PTA_PREFETCH_SSE},
{"k6", PROCESSOR_K6, PTA_MMX},
{"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
{"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
*************** incdec_operand (rtx op, enum machine_mod
*** 3771,3777 ****
{
/* On Pentium4, the inc and dec operations causes extra dependency on flag
registers, since carry flag is not set. */
! if (TARGET_PENTIUM4 && !optimize_size)
return 0;
return op == const1_rtx || op == constm1_rtx;
}
--- 3818,3824 ----
{
/* On Pentium4, the inc and dec operations causes extra dependency on flag
registers, since carry flag is not set. */
! if ((TARGET_PENTIUM4 || TARGET_NOCONA) && !optimize_size)
return 0;
return op == const1_rtx || op == constm1_rtx;
}
*************** ix86_issue_rate (void)
*** 12074,12079 ****
--- 12121,12127 ----
case PROCESSOR_PENTIUM4:
case PROCESSOR_ATHLON:
case PROCESSOR_K8:
+ case PROCESSOR_NOCONA:
return 3;
default:
cvs server: I know nothing about config/i386/i386.c.~1.660.~
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.382
diff -c -d -p -r1.382 i386.h
*** config/i386/i386.h 16 Mar 2004 23:29:22 -0000 1.382
--- config/i386/i386.h 1 Apr 2004 19:26:44 -0000
*************** extern int target_flags;
*** 219,224 ****
--- 219,225 ----
#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
+ #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TUNEMASK (1 << ix86_tune)
extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
*************** extern int x86_prefetch_sse;
*** 606,611 ****
--- 607,614 ----
builtin_define ("__tune_k8__"); \
else if (TARGET_PENTIUM4) \
builtin_define ("__tune_pentium4__"); \
+ else if (TARGET_NOCONA) \
+ builtin_define ("__tune_nocona__"); \
\
if (TARGET_MMX) \
builtin_define ("__MMX__"); \
*************** extern int x86_prefetch_sse;
*** 674,679 ****
--- 677,687 ----
builtin_define ("__pentium4"); \
builtin_define ("__pentium4__"); \
} \
+ else if (ix86_arch == PROCESSOR_NOCONA) \
+ { \
+ builtin_define ("__nocona"); \
+ builtin_define ("__nocona__"); \
+ } \
} \
while (0)
*************** enum processor_type
*** 2944,2949 ****
--- 2952,2958 ----
PROCESSOR_ATHLON,
PROCESSOR_PENTIUM4,
PROCESSOR_K8,
+ PROCESSOR_NOCONA,
PROCESSOR_max
};