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new mips type attributes: mtc1, mfc1


This is the fourth patch for expanding the type attributes for the SB-1 DFA
scheduler.  This is the last one I am planning on submitting for now.  The
actual SB-1 DFA scheduler will be next.

xfer is currently used for a number of different instructions types:
coprocessor 0 moves, which are typically memory instructions; coprocessor 1
moves, which are typically FP instructions; FP status register moves, which
are actually multi-insn sequences (no ctc1/cfc1 support needed here); and
coprocessor 2 and 3 moves which are often unimplemented.  The mtc1/mfc1
instructions are the only important ones.  So I have split those off from xfer.
The FP status register moves were changed to type multi.  xfer now is for the
coprocessor 0, 2, and 3 moves only.  Changes to constraint strings will be
necessary to separate cp0 from cp2 and cp3.  This didn't seem worthwhile.

There were two places where FP status registers moves had a length of 4.  I
fixed them to be 8 (move from) and 12 (move to).  The former is emitted by
mips_output_move, and the latter is generated by a secondary reload.

It is unclear how to fix the schedulers to handle the new xfer/mtc1/mfc1 types.
My assumption is that xfer will execute on the memory unit, and mtc1/mfc1 will
execute on the FP unit.  I have low confidence with this assumption, so I added
??? comments everywhere I made such an assumption.

The 9000.md file I handled differently.  It has xfer and FP condmove as both
executing on the memory unit.  Thus I assumed that mtc1/mfc1 were also
executed on the memory unit.  The memory unit apparently has access to both
integer and FP register on this target, which is consistent with how integer
and FP loads are handled.

sr71k.md tried to use modes to distinguish between mtc1 and mfc1, which isn't
quite right.  This was fixed to use mtc1 and mfc1 directly without the mode
checks.  This will be a behavioural change, but should be an improvement.

In addition to the xfer changes, I improved the comments for the condmove,
arith, and const types to try to eliminate some ambiguity.

I noticed that there are potential problems with condmove.  Currently, this
is used for 4 different types of instructions.  Integer reg moves based on
integer reg tests.  Integer moves based on FP condition codes.  FP reg moves
based on integer reg tests.  FP reg moves based on FP condition codes.  My
SR71k and SB-1 docs are a bit ambiguous here, so I just added ??? comments
to point out potential problems in the DFA schedulers.

If I am reading my SR71k docs correctly, only the first type (movn/movz) is
executed on the integer units, with the last 3 types all executed on the FP
units.  If that is true, then the sr71k.md ir_sr70_condmove reservation is
wrong.  However, my docs are a bit ambiguous, so I didn't try to fix this.

My SB-1 docs are contradictory, so I will have to ask the customer for
clarification here.

For the r5400 the current pattern may be right, as there is no separate
FP unit.

This was tested with a mips-elf cross build and gcc make check.  Ada and
objective C were disabled because they don't build.

Comments?
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com
2004-03-18  James E Wilson  <wilson@specifixinc.com>

	* config/mips/mips.md (movesi_internal): Change d/z and z/d
	alternatives to type multi, and change lengths to 8 and 12.
	(movecc): Change d/z alternative to type multi.
	(type): Add to condmove, const, arith comments.  Split off mtc1
	and mfc1 types from xfer.  Fix all uses.
	* config/mips/5400.md (ir_vr54_xfer): New.
	(ir_vr54_condmove): Add comment.
	(ir_vr54_mxc1): Renamed from ir_vr54_xfer.  Use mtc1 and mfc1 instead
	of xfer.
	* config/mips/5500.md (ir_vr55_xfer): New.
	(ir_vr55_condmove): Add comment.
	(ir_vr55_mxc1): Renamed from ir_vr55_xfer.  Use mtc1 and mfc1 instead
	of xfer.
	* config/mips/7000.md (rm7_int_other): Add comment.
	(rm7_xfer): New.
	(rm7_imxc1): Renamed from rm7_ixfer.  Use mtc1 and mfc1 instead of
	xfer.
	* config/mips/9000.md (rm9k_xfer): Add comment.  Add mtc1 and mfc1.
	* config/mips/sr71k.md (ir_sr70_xfer): New.
	(ir_sr70_condmove): Add comment.
	(ir_sr70_mfc1): Renamed from ir_sr70_xfer_from.  Use mfc1 not xfer.
	(ir_sr70_mtc1): Renamed from ir_sr70_xfer_to.  Use mtc1 not xfer.
	
Index: 5400.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5400.md,v
retrieving revision 1.6
diff -u -r1.6 5400.md
--- 5400.md	18 Mar 2004 23:47:31 -0000	1.6
+++ 5400.md	19 Mar 2004 02:29:30 -0000
@@ -39,18 +39,24 @@
        (eq_attr "type" "fpstore,fpidxstore"))
   "vr54_mem")
 
+;; ??? This is a guess.
+(define_insn_reservation "ir_vr54_xfer" 1
+  (and (eq_attr "cpu" "r5400")
+       (eq_attr "type" "xfer"))
+  "vr54_mem")
 
 ;; This reservation is for conditional move based on integer
 ;; or floating point CC.
+;; ??? Condmove matches both int reg and FP reg conditional moves.
 (define_insn_reservation "ir_vr54_condmove" 4
   (and (eq_attr "cpu" "r5400")
        (eq_attr "type" "condmove"))
   "vr54_dp0|vr54_dp1")
 
 ;; Move to/from FPU registers
-(define_insn_reservation "ir_vr54_xfer" 2
+(define_insn_reservation "ir_vr54_mxc1" 2
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mtc1,mfc1"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_hilo" 1
Index: 5500.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5500.md,v
retrieving revision 1.6
diff -u -r1.6 5500.md
--- 5500.md	18 Mar 2004 23:47:31 -0000	1.6
+++ 5500.md	19 Mar 2004 02:29:31 -0000
@@ -36,17 +36,24 @@
        (eq_attr "type" "store,fpstore,fpidxstore"))
   "vr55_mem")
 
+;; ??? This is a guess.
+(define_insn_reservation "ir_vr55_xfer" 1
+  (and (eq_attr "cpu" "r5500")
+       (eq_attr "type" "xfer"))
+  "vr55_mem")
+
 ;; This reservation is for conditional move based on integer
 ;; or floating point CC.
+;; ??? Condmove matches both int reg and FP reg conditional moves.
 (define_insn_reservation "ir_vr55_condmove" 2
   (and (eq_attr "cpu" "r5500")
        (eq_attr "type" "condmove"))
   "vr55_dp0|vr55_dp1")
 
 ;; Move to/from FPU registers
-(define_insn_reservation "ir_vr55_xfer" 2
+(define_insn_reservation "ir_vr55_mxc1" 2
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mtc1,mfc1"))
   "vr55_dp0|vr55_dp1")
 
 (define_insn_reservation "ir_vr55_hilo" 2
Index: 7000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/7000.md,v
retrieving revision 1.5
diff -u -r1.5 7000.md
--- 7000.md	18 Mar 2004 23:47:31 -0000	1.5
+++ 7000.md	19 Mar 2004 02:29:31 -0000
@@ -86,6 +86,7 @@
 ;; Describe instruction reservations for integer operations.
 ;;
 
+;; ??? Condmove matches both int reg and FP reg conditional moves.
 (define_insn_reservation "rm7_int_other" 1
 			 (and (eq_attr "cpu" "r7000")
 			      (eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
@@ -99,6 +100,11 @@
 				         (eq_attr "type" "store,fpstore,fpidxstore"))
 			 "rm7_imem")
 
+;; ??? This is a guess.
+(define_insn_reservation "rm7_xfer" 1 (and (eq_attr "cpu" "r7000")
+					   (eq_attr "type" "xfer"))
+			 "rm7_imem")
+
 (define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
 					   (and (eq_attr "type" "idiv")
 						(eq_attr "mode" "SI")))
@@ -141,8 +147,8 @@
 			 "rm7_impydiv")
 
 ;; Move to/from fp coprocessor.
-(define_insn_reservation "rm7_ixfer" 2 (and (eq_attr "cpu" "r7000")
-					(eq_attr "type" "xfer"))
+(define_insn_reservation "rm7_imxc1" 2 (and (eq_attr "cpu" "r7000")
+					(eq_attr "type" "mtc1,mfc1"))
 			 "rm7_iaddsub")
 
 (define_insn_reservation "rm7_ibr" 3 (and (eq_attr "cpu" "r7000")
Index: 9000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/9000.md,v
retrieving revision 1.5
diff -u -r1.5 9000.md
--- 9000.md	18 Mar 2004 23:47:31 -0000	1.5
+++ 9000.md	19 Mar 2004 02:29:31 -0000
@@ -96,9 +96,10 @@
        (eq_attr "type" "mthilo"))
   "rm9k_f_int")
 
+;; ??? The mtc1 and mfc1 handling is a guess.
 (define_insn_reservation "rm9k_xfer" 2
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "xfer,mtc1,mfc1"))
   "rm9k_m")
 
 (define_insn_reservation "rm9k_fquick" 2
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.227
diff -u -r1.227 mips.md
--- mips.md	18 Mar 2004 23:47:31 -0000	1.227
+++ mips.md	19 Mar 2004 02:29:41 -0000
@@ -101,12 +101,14 @@
 ;; fpidxstore	floating point indexed store
 ;; prefetch	memory prefetch (register + offset)
 ;; prefetchx	memory indexed prefetch (register + register)
-;; condmove	conditional moves
+;; condmove	conditional moves, all 4 types gpr/icc,gpr/fcc,fpr/icc,fpr/fcc
 ;; xfer		transfer to/from coprocessor
+;; mtc1		transfer to FP (coprocessor 1)
+;; mfc1		transfer from FP (coprocessor 1)
 ;; mthilo	transfer to hi/lo registers
 ;; mfhilo	transfer from hi/lo registers
-;; const	load constant
-;; arith	integer arithmetic and logical instructions
+;; const	load constant, arith insns that need special length calculation
+;; arith	integer arithmetic and logical instructions, and lui
 ;; shift	integer shift instructions
 ;; slt		set less than instructions
 ;; clz		the clz and clo instructions
@@ -128,7 +130,7 @@
 ;; multi	multiword sequence (or user asm statements)
 ;; nop		no operation
 (define_attr "type"
-  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mtc1,mfc1,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
   (cond [(eq_attr "jal" "!unset") (const_string "call")
 	 (eq_attr "got" "load") (const_string "load")]
 	(const_string "unknown")))
@@ -231,7 +233,7 @@
 	      (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
 	 (const_string "delay")
 
-	 (and (eq_attr "type" "xfer")
+	 (and (eq_attr "type" "xfer,mtc1,mfc1")
 	      (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
 	 (const_string "delay")
 
@@ -461,13 +463,15 @@
   (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
   3 0)
 
+;; ??? The mtc1,mfc1 handling is a guess.
 (define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fabs,fneg,fmove")
+  (and (eq_attr "type" "fabs,fneg,fmove,mtc1,mfc1")
        (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
   2 0)
 
+;; ??? The mtc1,mfc1 handling is a guess.
 (define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
+  (and (eq_attr "type" "fabs,fneg,fmove,mtc1,mfc1") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
   1 0)
 
 (define_function_unit "mult" 1 1
@@ -592,8 +596,9 @@
   (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
   3 3)
 
+;; ??? The mtc1,mfc1 handling is a guess.
 (define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "fcmp,fabs,fneg,fmove") (eq_attr "cpu" "r4300"))
+  (and (eq_attr "type" "fcmp,fabs,fneg,fmove,mtc1,mfc1") (eq_attr "cpu" "r4300"))
   1 1)
 
 (define_function_unit "imuldiv" 1 0
@@ -4560,7 +4565,7 @@
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,mfhilo,mthilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,const,const,load,store,fmove,mtc1,fpload,mfc1,fpstore,mthilo,mfhilo,mthilo,xfer,load,xfer,store")
    (set_attr "mode"	"DI")
    (set_attr "length"	"4,*,*,*,*,4,4,*,4,*,4,4,4,8,*,8,*")])
 
@@ -4684,9 +4689,9 @@
    && (register_operand (operands[0], SImode)
        || reg_or_0_operand (operands[1], SImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,mfhilo,mthilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,const,const,load,store,fmove,mtc1,fpload,mfc1,fpstore,multi,multi,mthilo,mfhilo,mthilo,xfer,load,xfer,store")
    (set_attr "mode"	"SI")
-   (set_attr "length"	"4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,4,*,4,*")])
+   (set_attr "length"	"4,*,*,*,*,4,4,*,4,*,8,12,4,4,4,4,*,4,*")])
 
 (define_insn "*movsi_mips16"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m,*d")
@@ -4802,7 +4807,7 @@
 	(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
   "ISA_HAS_8CC && TARGET_HARD_FLOAT"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
+  [(set_attr "type"	"multi,arith,load,store,mfc1,mtc1,fmove,fpload,fpstore")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8,4,*,*,4,4,4,*,*")])
 
@@ -4965,7 +4970,7 @@
     mov.s\t%0,%1
     mt%0\t%1
     mf%1\t%0"
-  [(set_attr "type"	"arith,arith,load,store,xfer,xfer,fmove,mthilo,mfhilo")
+  [(set_attr "type"	"arith,arith,load,store,mfc1,mtc1,fmove,mthilo,mfhilo")
    (set_attr "mode"	"HI")
    (set_attr "length"	"4,4,*,*,4,4,4,4,4")])
 
@@ -5075,7 +5080,7 @@
     mov.s\t%0,%1
     mt%0\t%1
     mf%1\t%0"
-  [(set_attr "type"	"arith,arith,load,store,xfer,xfer,fmove,mthilo,mfhilo")
+  [(set_attr "type"	"arith,arith,load,store,mfc1,mtc1,fmove,mthilo,mfhilo")
    (set_attr "mode"	"QI")
    (set_attr "length"	"4,4,*,*,4,4,4,4,4")])
 
@@ -5146,7 +5151,7 @@
    && (register_operand (operands[0], SFmode)
        || reg_or_0_operand (operands[1], SFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+  [(set_attr "type"	"fmove,mtc1,fpload,fpstore,mtc1,mfc1,arith,load,store")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4,4,*,*,4,4,4,*,*")])
 
@@ -5191,7 +5196,7 @@
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+  [(set_attr "type"	"fmove,mtc1,fpload,fpstore,mtc1,mfc1,arith,load,store")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4,4,*,*,4,4,4,*,*")])
 
@@ -5202,7 +5207,7 @@
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
+  [(set_attr "type"	"fmove,mtc1,fpload,fpstore,mtc1,mfc1,arith,load,store")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4,8,*,*,8,8,8,*,*")])
 
@@ -5213,7 +5218,7 @@
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,load,store,xfer,xfer,fmove")
+  [(set_attr "type"	"arith,load,store,mfc1,mtc1,fmove")
    (set_attr "mode"	"DF")
    (set_attr "length"	"8,*,*,4,4,4")])
 
@@ -5264,7 +5269,7 @@
   operands[0] = mips_subword (operands[0], 0);
   return mips_output_move (operands[0], operands[1]);
 }
-  [(set_attr "type"	"xfer,fpload")
+  [(set_attr "type"	"mtc1,fpload")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
 
@@ -5280,7 +5285,7 @@
   operands[0] = mips_subword (operands[0], 1);
   return mips_output_move (operands[0], operands[1]);
 }
-  [(set_attr "type"	"xfer,fpload")
+  [(set_attr "type"	"mtc1,fpload")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
 
@@ -5295,7 +5300,7 @@
   operands[1] = mips_subword (operands[1], 1);
   return mips_output_move (operands[0], operands[1]);
 }
-  [(set_attr "type"	"xfer,fpstore")
+  [(set_attr "type"	"mfc1,fpstore")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
 
Index: sr71k.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/sr71k.md,v
retrieving revision 1.8
diff -u -r1.8 sr71k.md
--- sr71k.md	18 Mar 2004 23:47:31 -0000	1.8
+++ sr71k.md	19 Mar 2004 02:29:42 -0000
@@ -150,6 +150,12 @@
                                (eq_attr "type" "store"))
                          "ri_mem")
 
+;; ??? This is a guess.
+(define_insn_reservation "ir_sr70_xfer"
+                               1
+                          (and (eq_attr "cpu" "sr71000")
+                               (eq_attr "type" "xfer"))
+                         "ri_mem")
 
 ;;
 ;; float loads/stores flow through both cpu and cp1...
@@ -169,6 +175,7 @@
 
 ;; This reservation is for conditional move based on integer
 ;; or floating point CC.
+;; ??? Condmove matches both int reg and FP reg conditional moves.
 (define_insn_reservation "ir_sr70_condmove"
                                4
                           (and (eq_attr "cpu" "sr71000")
@@ -178,18 +185,16 @@
 ;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
 ;; are different. Like float load/store, these insns use multiple
 ;; resources simultaneously
-(define_insn_reservation "ir_sr70_xfer_from"
+(define_insn_reservation "ir_sr70_mfc1"
                                6
                           (and (eq_attr "cpu" "sr71000")
-                               (and (eq_attr "type" "xfer")
-                                    (eq_attr "mode" "!SF,DF,FPSW")))
+                               (eq_attr "type" "mfc1"))
                          "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
 
-(define_insn_reservation "ir_sr70_xfer_to"
+(define_insn_reservation "ir_sr70_mtc1"
                                9
                           (and (eq_attr "cpu" "sr71000")
-                               (and (eq_attr "type" "xfer")
-                                    (eq_attr "mode" "SF,DF")))
+                               (eq_attr "type" "mtc1"))
                          "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
 
 (define_insn_reservation "ir_sr70_hilo"

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