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new mips type attributes: mthilo, mfhilo, trap, fmove


This is the third patch for expanding the type attributes for the SB-1 DFA
scheduler.

This combines a number of unrelated small changes.

This splits hilo into mthilo and mfhilo.  This allows a few simplications.
It would be even better to have mthi/mtlo as separate types, but that requires
hacking constraints, and I didn't want to risk that.

This deletes the icmp type.  This was last used in gcc-2.1 for the cc0
based compare patterns.  These patterns were converted to use CCmode in gcc-2.2
and the icmp type has been unused since.

This adds the trap type.  Currently, the trap insns have unknown type, which
prevents us from scheduling them.  trap presumably schedules same as slt,
except that it generates a trap instead of setting a result register, so I
added it to the same reservation as arith for all targets.

This splits the move type into fmove and arith.  move is currently used for
both integer and FP register moves which are rather different instructions.
Integer register moves will execute on ALU units, and FP register moves will
execute on FP units.  There is no need for an integer move type, as this is
just daddu/addu/or, and hence just a regular arith instruction.

There was one place where move was used for a FP status register access, I
changed it to xfer to match the other similar places.

There were a number of places where move was used with a constant source in
addition to a reg, contradicting the comments, but there is no problem now
that the arith type is used.

For scheduling purposes, I assume fmove schedules same as fabs and fneg.
This is true for the sr71k and SB-1, and very likely true for the other
targets.

I sorted the comments describing types so that they match the same order the
types are defined in.

This was tested with a mips-elf cross build and gcc make check.  Ada and
objective C were disabled because they don't build.

Comments?
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com
2004-03-17  James E Wilson  <wilson@specifixinc.com>

	* config/mips/mips.md (type): Split move into arith and fmove.  Split
	hilo into mthilo and mfhilo.  Add trap.  Delete icmp.  Fix all uses.
	* config/mips/5400.md (ir_vr54_hilo, ir_vr54_arith, ir_vr54_fabs):
	Likewise.
	* config/mips/5500.md (ir_vr55_hilo, ir_vr55_arith, ir_vr55_fabs):
	Likewise.
	* config/mips/7000.md (rm7_int_other, rm7_mthilo, rm7_mfhilo,
	rm7_fp_quick): Likewise.
	* config/mips/9000.md (rm9k_int, rm9k_mfhilo, rm9k_mthilo,
	rm9k_fquick): Likewise.
	* config/mips/sr71k.md (ir_sr70_hilo, ir_sr70_arith, ir_sr70_fabs):
	Likewise.
	(ir_sr70_icmp): Delete.

Index: 5400.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5400.md,v
retrieving revision 1.5
diff -p -u -r1.5 5400.md
--- 5400.md	17 Mar 2004 09:33:44 -0000	1.5
+++ 5400.md	18 Mar 2004 06:17:04 -0000
@@ -55,12 +55,12 @@
 
 (define_insn_reservation "ir_vr54_hilo" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "hilo"))
+       (eq_attr "type" "mthilo,mfhilo"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_arith" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "move,arith,shift,slt,clz,const,icmp,nop"))
+       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_imul_si" 3
@@ -135,7 +135,7 @@
 
 (define_insn_reservation "ir_vr54_fabs" 2
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "fabs,fneg"))
+       (eq_attr "type" "fabs,fneg,fmove"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_fcmp" 2
Index: 5500.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5500.md,v
retrieving revision 1.5
diff -p -u -r1.5 5500.md
--- 5500.md	17 Mar 2004 09:33:44 -0000	1.5
+++ 5500.md	18 Mar 2004 06:17:05 -0000
@@ -51,12 +51,12 @@
 
 (define_insn_reservation "ir_vr55_hilo" 2
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "hilo"))
+       (eq_attr "type" "mthilo,mfhilo"))
   "vr55_dp0|vr55_dp1")
 
 (define_insn_reservation "ir_vr55_arith" 1
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "move,arith,shift,slt,clz,const,icmp,nop"))
+       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
   "vr55_dp0|vr55_dp1")
 
 (define_insn_reservation "ir_vr55_imul_si" 3
@@ -133,7 +133,7 @@
 
 (define_insn_reservation "ir_vr55_fabs" 2
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "fabs,fneg"))
+       (eq_attr "type" "fabs,fneg,fmove"))
   "vr55_fp")
 
 (define_insn_reservation "ir_vr55_fcmp" 2
Index: 7000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/7000.md,v
retrieving revision 1.4
diff -p -u -r1.4 7000.md
--- 7000.md	17 Mar 2004 09:33:44 -0000	1.4
+++ 7000.md	18 Mar 2004 06:17:05 -0000
@@ -88,7 +88,7 @@
 
 (define_insn_reservation "rm7_int_other" 1
 			 (and (eq_attr "cpu" "r7000")
-			      (eq_attr "type" "arith,shift,slt,clz,const,move,condmove,icmp,nop"))
+			      (eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
 			 "rm7_iaddsub")
 
 (define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
@@ -132,14 +132,12 @@
 ;; Move to/from HI/LO.
 (define_insn_reservation "rm7_mthilo" 3
 			 (and (eq_attr "cpu" "r7000")
-			      (and (eq_attr "type" "hilo")
-				   (match_operand 0 "hilo_operand" "")))
+			      (eq_attr "type" "mthilo"))
 			 "rm7_impydiv")
 
 (define_insn_reservation "rm7_mfhilo" 1
 			 (and (eq_attr "cpu" "r7000")
-			      (and (eq_attr "type" "hilo")
-				   (not (match_operand 0 "hilo_operand" ""))))
+			      (eq_attr "type" "mfhilo"))
 			 "rm7_impydiv")
 
 ;; Move to/from fp coprocessor.
@@ -156,7 +154,7 @@
 ;;
 (define_insn_reservation "rm7_fp_quick" 4
 			 (and (eq_attr "cpu" "r7000")
-			      (eq_attr "type" "fneg,fcmp,fabs"))
+			      (eq_attr "type" "fneg,fcmp,fabs,fmove"))
 			 "rm7_fpadd")
 
 (define_insn_reservation "rm7_fp_other" 4
Index: 9000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/9000.md,v
retrieving revision 1.4
diff -p -u -r1.4 9000.md
--- 9000.md	17 Mar 2004 09:33:44 -0000	1.4
+++ 9000.md	18 Mar 2004 06:17:05 -0000
@@ -52,7 +52,7 @@
 
 (define_insn_reservation "rm9k_int" 1
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "move,arith,shift,slt,clz,const,icmp,nop"))
+       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
   "rm9k_any1 | rm9k_any2")
 
 (define_insn_reservation "rm9k_int_cmove" 2
@@ -88,14 +88,12 @@
 
 (define_insn_reservation "rm9k_mfhilo" 1
   (and (eq_attr "cpu" "r9000")
-       (and (eq_attr "type" "hilo")
-	    (not (match_operand 0 "hilo_operand" ""))))
+       (eq_attr "type" "mfhilo"))
   "rm9k_f_int")
 
 (define_insn_reservation "rm9k_mthilo" 5
   (and (eq_attr "cpu" "r9000")
-       (and (eq_attr "type" "hilo")
-	    (match_operand 0 "hilo_operand" "")))
+       (eq_attr "type" "mthilo"))
   "rm9k_f_int")
 
 (define_insn_reservation "rm9k_xfer" 2
@@ -105,7 +103,7 @@
 
 (define_insn_reservation "rm9k_fquick" 2
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "fabs,fneg,fcmp"))
+       (eq_attr "type" "fabs,fneg,fcmp,fmove"))
   "rm9k_f_float")
 
 (define_insn_reservation "rm9k_fcmove" 2
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.226
diff -p -u -r1.226 mips.md
--- mips.md	17 Mar 2004 09:33:44 -0000	1.226
+++ mips.md	18 Mar 2004 06:17:15 -0000
@@ -101,19 +101,20 @@
 ;; fpidxstore	floating point indexed store
 ;; prefetch	memory prefetch (register + offset)
 ;; prefetchx	memory indexed prefetch (register + register)
-;; move		data movement within same register set
 ;; condmove	conditional moves
 ;; xfer		transfer to/from coprocessor
-;; hilo		transfer of hi/lo registers
+;; mthilo	transfer to hi/lo registers
+;; mfhilo	transfer from hi/lo registers
+;; const	load constant
 ;; arith	integer arithmetic and logical instructions
 ;; shift	integer shift instructions
-;; clz		the clz and clo instructions
 ;; slt		set less than instructions
-;; const	load constant
+;; clz		the clz and clo instructions
+;; trap		trap if instructions
 ;; imul		integer multiply
 ;; imadd	integer multiply-add
 ;; idiv		integer divide
-;; icmp		integer compare
+;; fmove	floating point register move
 ;; fadd		floating point add/subtract
 ;; fmul		floating point multiply
 ;; fmadd	floating point multiply-add
@@ -127,7 +128,7 @@
 ;; multi	multiword sequence (or user asm statements)
 ;; nop		no operation
 (define_attr "type"
-  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,shift,slt,clz,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
   (cond [(eq_attr "jal" "!unset") (const_string "call")
 	 (eq_attr "got" "load") (const_string "load")]
 	(const_string "unknown")))
@@ -243,9 +244,8 @@
 	      (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
 	 (const_string "hilo")
 
-	 (and (eq_attr "type" "hilo")
-	      (and (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0))
-		   (match_operand 1 "hilo_operand" "")))
+	 (and (eq_attr "type" "mfhilo")
+	      (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
 	 (const_string "hilo")]
 	(const_string "none")))
 
@@ -324,7 +324,7 @@
 (define_function_unit "memory"   1 0 (eq_attr "type" "xfer") 2 0)
 
 (define_function_unit "imuldiv"  1 0
-  (eq_attr "type" "hilo")
+  (eq_attr "type" "mthilo,mfhilo")
   1 3)
 
 (define_function_unit "imuldiv"  1 0
@@ -339,7 +339,7 @@
 ;; selecting instructions to between the two instructions.
 
 (define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "hilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
+  (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
   1 5)
 
 (define_function_unit "imuldiv"  1 0
@@ -462,12 +462,12 @@
   3 0)
 
 (define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fabs,fneg")
+  (and (eq_attr "type" "fabs,fneg,fmove")
        (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
   2 0)
 
 (define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
+  (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
   1 0)
 
 (define_function_unit "mult" 1 1
@@ -593,7 +593,7 @@
   3 3)
 
 (define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
+  (and (eq_attr "type" "fcmp,fabs,fneg,fmove") (eq_attr "cpu" "r4300"))
   1 1)
 
 (define_function_unit "imuldiv" 1 0
@@ -639,7 +639,8 @@
     return "break 0";
   else
     return "break";
-})
+}
+  [(set_attr "type"	"trap")])
 
 (define_expand "conditional_trap"
   [(trap_if (match_operator 0 "cmp_op"
@@ -662,7 +663,8 @@
                              (match_operand:SI 2 "arith_operand" "dI")])
 	    (const_int 0))]
   "ISA_HAS_COND_TRAP"
-  "t%C0\t%z1,%z2")
+  "t%C0\t%z1,%z2"
+  [(set_attr "type"	"trap")])
 
 (define_insn ""
   [(trap_if (match_operator 0 "trap_cmp_op"
@@ -670,7 +672,8 @@
                              (match_operand:DI 2 "arith_operand" "dI")])
 	    (const_int 0))]
   "TARGET_64BIT && ISA_HAS_COND_TRAP"
-  "t%C0\t%z1,%z2")
+  "t%C0\t%z1,%z2"
+  [(set_attr "type"	"trap")])
 
 ;;
 ;;  ....................
@@ -4535,7 +4538,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,arith,load,store,hilo,hilo,hilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,arith,load,store,mthilo,mfhilo,mthilo,xfer,load,xfer,store")
    (set_attr "mode"	"DI")
    (set_attr "length"   "8,16,*,*,8,8,8,8,*,8,*")])
 
@@ -4546,7 +4549,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,move,move,arith,arith,load,store,hilo")
+  [(set_attr "type"	"arith,arith,arith,arith,arith,load,store,mfhilo")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8,8,8,8,12,*,*,8")])
 
@@ -4557,7 +4560,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,const,const,load,store,move,xfer,fpload,xfer,fpstore,hilo,hilo,hilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,mfhilo,mthilo,xfer,load,xfer,store")
    (set_attr "mode"	"DI")
    (set_attr "length"	"4,*,*,*,*,4,4,*,4,*,4,4,4,8,*,8,*")])
 
@@ -4568,7 +4571,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,move,move,arith,arith,const,load,store,hilo")
+  [(set_attr "type"	"arith,arith,arith,arith,arith,const,load,store,mfhilo")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -4681,7 +4684,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], SImode)
        || reg_or_0_operand (operands[1], SImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,const,const,load,store,move,xfer,fpload,xfer,fpstore,xfer,xfer,hilo,hilo,hilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,mfhilo,mthilo,xfer,load,xfer,store")
    (set_attr "mode"	"SI")
    (set_attr "length"	"4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,4,*,4,*")])
 
@@ -4692,7 +4695,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,move,move,arith,arith,const,load,store,hilo")
+  [(set_attr "type"	"arith,arith,arith,arith,arith,const,load,store,mfhilo")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -4799,7 +4802,7 @@ dsrl\t%3,%3,1\n\
 	(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
   "ISA_HAS_8CC && TARGET_HARD_FLOAT"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,move,load,store,xfer,xfer,move,fpload,fpstore")
+  [(set_attr "type"	"xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8,4,*,*,4,4,4,*,*")])
 
@@ -4962,7 +4965,7 @@ dsrl\t%3,%3,1\n\
     mov.s\t%0,%1
     mt%0\t%1
     mf%1\t%0"
-  [(set_attr "type"	"move,arith,load,store,xfer,xfer,move,hilo,hilo")
+  [(set_attr "type"	"arith,arith,load,store,xfer,xfer,fmove,mthilo,mfhilo")
    (set_attr "mode"	"HI")
    (set_attr "length"	"4,4,*,*,4,4,4,4,4")])
 
@@ -4981,7 +4984,7 @@ dsrl\t%3,%3,1\n\
     lhu\t%0,%1
     sh\t%1,%0
     mf%1\t%0"
-  [(set_attr "type"	"move,move,move,arith,arith,load,store,hilo")
+  [(set_attr "type"	"arith,arith,arith,arith,arith,load,store,mfhilo")
    (set_attr "mode"	"HI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -5072,7 +5075,7 @@ dsrl\t%3,%3,1\n\
     mov.s\t%0,%1
     mt%0\t%1
     mf%1\t%0"
-  [(set_attr "type"	"move,arith,load,store,xfer,xfer,move,hilo,hilo")
+  [(set_attr "type"	"arith,arith,load,store,xfer,xfer,fmove,mthilo,mfhilo")
    (set_attr "mode"	"QI")
    (set_attr "length"	"4,4,*,*,4,4,4,4,4")])
 
@@ -5091,7 +5094,7 @@ dsrl\t%3,%3,1\n\
     lbu\t%0,%1
     sb\t%1,%0
     mf%1\t%0"
-  [(set_attr "type"	"move,move,move,arith,arith,load,store,hilo")
+  [(set_attr "type"	"arith,arith,arith,arith,arith,load,store,mfhilo")
    (set_attr "mode"	"QI")
    (set_attr "length"	"4,4,4,4,8,*,*,4")])
 
@@ -5143,7 +5146,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], SFmode)
        || reg_or_0_operand (operands[1], SFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,xfer,fpload,fpstore,xfer,xfer,move,load,store")
+  [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4,4,*,*,4,4,4,*,*")])
 
@@ -5154,7 +5157,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], SFmode)
        || reg_or_0_operand (operands[1], SFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,load,store")
+  [(set_attr "type"	"arith,load,store")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4,*,*")])
 
@@ -5165,7 +5168,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,move,move,load,store")
+  [(set_attr "type"	"arith,arith,arith,load,store")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4,4,4,*,*")])
 
@@ -5188,7 +5191,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,xfer,fpload,fpstore,xfer,xfer,move,load,store")
+  [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4,4,*,*,4,4,4,*,*")])
 
@@ -5199,7 +5202,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,xfer,fpload,fpstore,xfer,xfer,move,load,store")
+  [(set_attr "type"	"fmove,xfer,fpload,fpstore,xfer,xfer,arith,load,store")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4,8,*,*,8,8,8,*,*")])
 
@@ -5210,7 +5213,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,load,store,xfer,xfer,move")
+  [(set_attr "type"	"arith,load,store,xfer,xfer,fmove")
    (set_attr "mode"	"DF")
    (set_attr "length"	"8,*,*,4,4,4")])
 
@@ -5221,7 +5224,7 @@ dsrl\t%3,%3,1\n\
    && (register_operand (operands[0], DFmode)
        || register_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"move,move,move,load,store")
+  [(set_attr "type"	"arith,arith,arith,load,store")
    (set_attr "mode"	"DF")
    (set_attr "length"	"8,8,8,*,*")])
 
Index: sr71k.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/sr71k.md,v
retrieving revision 1.7
diff -p -u -r1.7 sr71k.md
--- sr71k.md	17 Mar 2004 09:33:45 -0000	1.7
+++ sr71k.md	18 Mar 2004 06:17:15 -0000
@@ -195,13 +195,13 @@
 (define_insn_reservation "ir_sr70_hilo"
                                1
                           (and (eq_attr "cpu" "sr71000")
-                               (eq_attr "type" "hilo"))
+                               (eq_attr "type" "mthilo,mfhilo"))
                          "ri_insns")
 
 (define_insn_reservation "ir_sr70_arith"
                                1
                           (and (eq_attr "cpu" "sr71000")
-                               (eq_attr "type" "move,arith,shift,slt,clz,const"))
+                               (eq_attr "type" "arith,shift,slt,clz,const,trap"))
                          "ri_insns")
 
 ;; emulate repeat (dispatch stall) by spending extra cycle(s) in
@@ -236,12 +236,6 @@
                                     (eq_attr "mode" "DI")))
                          "ri_alux,ipu_alux,(ipu_macc_iter*70)")
 
-(define_insn_reservation "ir_sr70_icmp"
-                               1
-                          (and (eq_attr "cpu" "sr71000")
-                               (eq_attr "type" "icmp"))
-                         "ri_insns")
-
 ;; extra reservations of fpu_fpu are for repeat latency
 (define_insn_reservation "ir_sr70_fadd_sf"
                                8
@@ -298,7 +292,7 @@
 (define_insn_reservation "ir_sr70_fabs"
                                4
                           (and (eq_attr "cpu" "sr71000")
-                               (eq_attr "type" "fabs,fneg"))
+                               (eq_attr "type" "fabs,fneg,fmove"))
                          "rf_insn,fpu_fpu")
 
 (define_insn_reservation "ir_sr70_fcmp"

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