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new mips type attributes: shift, slt, clz


This is the second patch for expanding the type attributes for the SB-1 DFA
scheduler.

This splits arith into arith, shift, slt, and clz.  Arith now contains only
typical ALU operations such as ADD/SUB and AND/OR, and also LUI.  I don't
actually need slt and clz as different types, but it seemed more reasonable
to me to create two types for them instead of grouping them into one.

SB-1 does not have SEB/SEH instructions, so it wasn't clear what type to give
them.  I left them as arith.  They could perhaps be shift.  It depends on
how they get implemented.

I noticed some patterns emitting multiple instructions that had type arith.
I changed them to multi which I think is more reasonable.  I also added a
length attribute to one pattern that was missing it.  Almost all of these have
splitters, so this should have no practical effect for scheduling.

I eliminated the darith type.  It was used inconsistently, some DImode patterns
used darith and some used arith.  There wasn't any place that use darith
differently than arith.  Also, I wanted to avoid creating dshift and dclz
types.  So I got rid of darith.

I changed the hazard_nop to be type nop instead of arith.  The other nop
pattern already was type nop.  Since nop is typically tranlated to sll, and
shifts schedule differently than arith on SB-1, having hazard_nop be type
arith is a problem.

The const type seems to be used inconsistently.  Some places that load
constants use the const type, some use the arith type.  I didn't try to
decipher this.  I left these as arith which seems accurate, since they will
expand to either an addiu, ori, or lui in the vast majority of cases.

While developing this, I changed arith to old_arith and back again, to make
sure I looked at every use of the arith type.

This was tested with a mips-elf cross build and gcc make check.  libobjc
failed to build.  I get an abort in apply_args_size.  This was broken by Eric's
patch to FUNCTION_ARG_REGNO_P.  The problem is that FUNCTION_ARG_REGNO_P is
true for reg 45, however, there is no mode valid for reg 45 as per
HARD_REGNO_MODE_OK, so we end up hitting the mode == VOIDmode abort.  This
probably explains why we had the checks there to disable odd numbered
FP regs when using 32-bit FP regs.  Also, the ada library failed to build
because it couldn't find the newlib headers.  I just disabled ada and objective
C for this test to get past these problems.

Comments?
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com
2004-03-16  James E Wilson  <wilson@specifixinc.com>

	* config/mips/mips.md (zero_extendsidi2): Add length attribute.
	(hazard_nop): Change type to nop.
	(type): Split arith into arith, shift, slt, clz.  Delete darith.
	Fix all uses.  Change arith to multi if more than one insn emitted.
	* config/mips/5400.md (ir_vr54_arith): Likewise.
	* config/mips/5500.md (ir_vr55_arith): Likewise.
	* config/mips/7000.md (rm7_int_other): Likewise.
	* config/mips/9000.md (rm9k_int): Likewise.
	* config/mips/sr71k.md (ir_sr70_arith): Likewise.

Index: 5400.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5400.md,v
retrieving revision 1.4
diff -u -r1.4 5400.md
--- 5400.md	16 Mar 2004 02:11:41 -0000	1.4
+++ 5400.md	17 Mar 2004 02:15:31 -0000
@@ -60,7 +60,7 @@
 
 (define_insn_reservation "ir_vr54_arith" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
+       (eq_attr "type" "move,arith,shift,slt,clz,const,icmp,nop"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_imul_si" 3
Index: 5500.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5500.md,v
retrieving revision 1.4
diff -u -r1.4 5500.md
--- 5500.md	16 Mar 2004 02:11:41 -0000	1.4
+++ 5500.md	17 Mar 2004 02:15:31 -0000
@@ -56,7 +56,7 @@
 
 (define_insn_reservation "ir_vr55_arith" 1
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
+       (eq_attr "type" "move,arith,shift,slt,clz,const,icmp,nop"))
   "vr55_dp0|vr55_dp1")
 
 (define_insn_reservation "ir_vr55_imul_si" 3
Index: 7000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/7000.md,v
retrieving revision 1.2
diff -u -r1.2 7000.md
--- 7000.md	16 Mar 2004 02:11:41 -0000	1.2
+++ 7000.md	17 Mar 2004 02:15:31 -0000
@@ -88,7 +88,7 @@
 
 (define_insn_reservation "rm7_int_other" 1
 			 (and (eq_attr "cpu" "r7000")
-			      (eq_attr "type" "arith,darith,const,move,condmove,icmp,nop"))
+			      (eq_attr "type" "arith,shift,slt,clz,const,move,condmove,icmp,nop"))
 			 "rm7_iaddsub")
 
 (define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
Index: 9000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/9000.md,v
retrieving revision 1.2
diff -u -r1.2 9000.md
--- 9000.md	16 Mar 2004 02:11:41 -0000	1.2
+++ 9000.md	17 Mar 2004 02:15:31 -0000
@@ -52,7 +52,7 @@
 
 (define_insn_reservation "rm9k_int" 1
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
+       (eq_attr "type" "move,arith,shift,slt,clz,const,icmp,nop"))
   "rm9k_any1 | rm9k_any2")
 
 (define_insn_reservation "rm9k_int_cmove" 2
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.224
diff -u -r1.224 mips.md
--- mips.md	16 Mar 2004 02:11:41 -0000	1.224
+++ mips.md	17 Mar 2004 02:15:41 -0000
@@ -104,8 +104,10 @@
 ;; condmove	conditional moves
 ;; xfer		transfer to/from coprocessor
 ;; hilo		transfer of hi/lo registers
-;; arith	integer arithmetic instruction
-;; darith	double precision integer arithmetic instructions
+;; arith	integer arithmetic and logical instructions
+;; shift	integer shift instructions
+;; clz		the clz and clo instructions
+;; slt		set less than instructions
 ;; const	load constant
 ;; imul		integer multiply
 ;; imadd	integer multiply-add
@@ -124,7 +126,7 @@
 ;; multi	multiword sequence (or user asm statements)
 ;; nop		no operation
 (define_attr "type"
-  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,shift,slt,clz,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
   (cond [(eq_attr "jal" "!unset") (const_string "call")
 	 (eq_attr "got" "load") (const_string "load")]
 	(const_string "unknown")))
@@ -914,7 +916,7 @@
     ? "srl\t%3,%L0,31\;sll\t%M0,%M0,1\;sll\t%L0,%L1,1\;addu\t%M0,%M0,%3"
     : "addu\t%L0,%L1,%L2\;sltu\t%3,%L0,%L2\;addu\t%M0,%M1,%M2\;addu\t%M0,%M0,%3";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
 
@@ -988,7 +990,7 @@
    addu\t%L0,%L1,%2\;sltu\t%3,%L0,%2\;addu\t%M0,%M1,%3
    move\t%L0,%L1\;move\t%M0,%M1
    subu\t%L0,%L1,%n2\;sltu\t%3,%L0,%2\;subu\t%M0,%M1,1\;addu\t%M0,%M0,%3"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"12,8,16")])
 
@@ -1048,7 +1050,7 @@
   "@
     daddu\t%0,%z1,%2
     daddiu\t%0,%z1,%2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 ;; For the mips16, we need to recognize stack pointer additions
@@ -1280,7 +1282,7 @@
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
   "sltu\t%3,%L1,%L2\;subu\t%L0,%L1,%L2\;subu\t%M0,%M1,%M2\;subu\t%M0,%M0,%3"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
 
@@ -1346,7 +1348,7 @@
 		  (match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT"
   "dsubu\t%0,%1,%2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 (define_insn "subsi3_internal_2"
@@ -2862,7 +2864,7 @@
 	(clz:SI (match_operand:SI 1 "register_operand" "d")))]
   "ISA_HAS_CLZ_CLO"
   "clz\t%0,%1"
-  [(set_attr "type" "arith")
+  [(set_attr "type" "clz")
    (set_attr "mode" "SI")])
 
 (define_insn "clzdi2"
@@ -2870,7 +2872,7 @@
 	(clz:DI (match_operand:DI 1 "register_operand" "d")))]
   "ISA_HAS_DCLZ_DCLO"
   "dclz\t%0,%1"
-  [(set_attr "type" "arith")
+  [(set_attr "type" "clz")
    (set_attr "mode" "DI")])
 
 ;;
@@ -2914,7 +2916,7 @@
    (clobber (match_operand:SI 2 "register_operand" "=d"))]
   "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
   "subu\t%L0,%.,%L1\;subu\t%M0,%.,%M1\;sltu\t%2,%.,%L0\;subu\t%M0,%M0,%2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
 
@@ -2965,7 +2967,7 @@
   else
     return "nor\t%0,%.,%1";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 ;;
@@ -3033,7 +3035,7 @@
   "@
    and\t%0,%1,%2
    andi\t%0,%1,%x2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -3042,7 +3044,7 @@
 		(match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_MIPS16"
   "and\t%0,%2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 (define_expand "iorsi3"
@@ -3099,7 +3101,7 @@
   "@
    or\t%0,%1,%2
    ori\t%0,%1,%x2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -3108,7 +3110,7 @@
 		(match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_MIPS16"
   "or\t%0,%2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 (define_expand "xorsi3"
@@ -3168,7 +3170,7 @@
   "@
    xor\t%0,%1,%2
    xori\t%0,%1,%x2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -3204,7 +3206,7 @@
 		(not:DI (match_operand:DI 2 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "nor\t%0,%z1,%z2"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
 ;;
@@ -3244,7 +3246,7 @@
   "@
     sll\t%0,%1,0
     sw\t%1,%0"
-  [(set_attr "type" "darith,store")
+  [(set_attr "type" "shift,store")
    (set_attr "mode" "SI")
    (set_attr "extended_mips16" "yes,*")])
 
@@ -3255,7 +3257,7 @@
   "@
     sll\t%0,%1,0
     sh\t%1,%0"
-  [(set_attr "type" "darith,store")
+  [(set_attr "type" "shift,store")
    (set_attr "mode" "SI")
    (set_attr "extended_mips16" "yes,*")])
 
@@ -3266,7 +3268,7 @@
   "@
     sll\t%0,%1,0
     sb\t%1,%0"
-  [(set_attr "type" "darith,store")
+  [(set_attr "type" "shift,store")
    (set_attr "mode" "SI")
    (set_attr "extended_mips16" "yes,*")])
 
@@ -3278,7 +3280,7 @@
                                   (match_operand:DI 2 "small_int" "I"))))]
   "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
   "dsra\t%0,%1,%2"
-  [(set_attr "type" "darith")
+  [(set_attr "type" "shift")
    (set_attr "mode" "SI")])
 
 (define_insn ""
@@ -3287,7 +3289,7 @@
                                   (const_int 32))))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "dsra\t%0,%1,32"
-  [(set_attr "type" "darith")
+  [(set_attr "type" "shift")
    (set_attr "mode" "SI")])
 
 
@@ -3333,7 +3335,7 @@
                          (match_operand:DI 1 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "andi\t%0,%1,0xffff"
-  [(set_attr "type"     "darith")
+  [(set_attr "type"     "arith")
    (set_attr "mode"     "SI")])
 
 (define_insn ""
@@ -3342,7 +3344,7 @@
                          (match_operand:DI 1 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "andi\t%0,%1,0xff"
-  [(set_attr "type"     "darith")
+  [(set_attr "type"     "arith")
    (set_attr "mode"     "SI")])
 
 (define_insn ""
@@ -3351,7 +3353,7 @@
                          (match_operand:DI 1 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "andi\t%0,%1,0xff"
-  [(set_attr "type"     "darith")
+  [(set_attr "type"     "arith")
    (set_attr "mode"     "HI")])
 
 ;;
@@ -3375,8 +3377,9 @@
    (set (match_dup 0)
         (lshiftrt:DI (match_dup 0) (const_int 32)))]
   "operands[1] = gen_lowpart (DImode, operands[1]);"
-  [(set_attr "type" "arith")
-   (set_attr "mode" "DI")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "DI")
+   (set_attr "length" "8")])
 
 (define_insn "*zero_extendsidi2_mem"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -3574,7 +3577,7 @@
   "@
    sll\t%0,%1,0
    lw\t%0,%1"
-  [(set_attr "type" "arith,load")
+  [(set_attr "type" "shift,load")
    (set_attr "mode" "DI")
    (set_attr "extended_mips16" "yes,*")])
 
@@ -5405,7 +5408,7 @@
 
   return "sll\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"SI")])
 
 (define_insn "ashlsi3_internal1_extend"
@@ -5419,7 +5422,7 @@
 
   return "sll\t%0,%1,%2";
 }
-  [(set_attr "type"    "arith")
+  [(set_attr "type"    "shift")
    (set_attr "mode"    "DI")])
 
 
@@ -5437,7 +5440,7 @@
 
   return "sll\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -5522,7 +5525,7 @@
 %~2:\;\
 sll\t%L0,%L1,%2\n\
 %~3:"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"48")])
 
@@ -5538,7 +5541,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "sll\t%M0,%L1,%2\;move\t%L0,%.";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -5593,7 +5596,7 @@
 
   return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
 
@@ -5677,7 +5680,7 @@
 
   return "dsll\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -5694,7 +5697,7 @@
 
   return "dsll\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -5755,7 +5758,7 @@
 
   return "sra\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"SI")])
 
 (define_insn "ashrsi3_internal2"
@@ -5772,7 +5775,7 @@
 
   return "sra\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -5854,7 +5857,7 @@
 %~2:\;\
 sra\t%M0,%M1,%2\n\
 %~3:"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"48")])
 
@@ -5869,7 +5872,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -5924,7 +5927,7 @@
 
   return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
 
@@ -6008,7 +6011,7 @@
 
   return "dsra\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -6022,7 +6025,7 @@
 
   return "dsra\t%0,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -6082,7 +6085,7 @@
 
   return "srl\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"SI")])
 
 (define_insn "lshrsi3_internal2"
@@ -6099,7 +6102,7 @@
 
   return "srl\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -6204,7 +6207,7 @@
 %~2:\;\
 srl\t%M0,%M1,%2\n\
 %~3:"
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"48")])
 
@@ -6220,7 +6223,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "srl\t%L0,%M1,%2\;move\t%M0,%.";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -6275,7 +6278,7 @@
 
   return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
 }
-  [(set_attr "type"	"darith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
 
@@ -6359,7 +6362,7 @@
 
   return "dsrl\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -6373,7 +6376,7 @@
 
   return "dsrl\t%0,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"shift")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -6396,7 +6399,7 @@
 
   return "ror\t%0,%1,%2";
 }
-  [(set_attr "type"     "arith")
+  [(set_attr "type"     "shift")
    (set_attr "mode"     "SI")])
 
 (define_insn "rotrdi3"
@@ -6420,7 +6423,7 @@
 
   return "dror\t%0,%1,%2";
 }
-  [(set_attr "type"     "arith")
+  [(set_attr "type"     "shift")
    (set_attr "mode"     "DI")])
 
 
@@ -7035,7 +7038,7 @@
 	       (const_int 0)))]
   "!TARGET_MIPS16"
   "sltu\t%0,%1,1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn ""
@@ -7044,7 +7047,7 @@
 	       (const_int 0)))]
   "TARGET_MIPS16"
   "sltu\t%1,1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn "seq_di_zero"
@@ -7053,7 +7056,7 @@
 	       (const_int 0)))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "sltu\t%0,%1,1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -7062,7 +7065,7 @@
 	       (const_int 0)))]
   "TARGET_64BIT && TARGET_MIPS16"
   "sltu\t%1,1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn "seq_si"
@@ -7073,7 +7076,7 @@
   "@
    xor\t%0,%1,%2\;sltu\t%0,%0,1
    xori\t%0,%1,%2\;sltu\t%0,%0,1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
 
@@ -7099,7 +7102,7 @@
   "@
    xor\t%0,%1,%2\;sltu\t%0,%0,1
    xori\t%0,%1,%2\;sltu\t%0,%0,1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -7151,7 +7154,7 @@
 	       (const_int 0)))]
   "!TARGET_MIPS16"
   "sltu\t%0,%.,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn "sne_di_zero"
@@ -7160,7 +7163,7 @@
 	       (const_int 0)))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "sltu\t%0,%.,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn "sne_si"
@@ -7171,7 +7174,7 @@
   "@
     xor\t%0,%1,%2\;sltu\t%0,%.,%0
     xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
 
@@ -7197,7 +7200,7 @@
   "@
     xor\t%0,%1,%2\;sltu\t%0,%.,%0
     xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -7247,7 +7250,7 @@
 	       (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
   "!TARGET_MIPS16"
   "slt\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn ""
@@ -7256,7 +7259,7 @@
 	       (match_operand:SI 2 "register_operand" "d")))]
   "TARGET_MIPS16"
   "slt\t%2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn "sgt_di"
@@ -7265,7 +7268,7 @@
 	       (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "slt\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -7274,7 +7277,7 @@
 	       (match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_MIPS16"
   "slt\t%2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_expand "sge"
@@ -7305,7 +7308,7 @@
 	       (match_operand:SI 2 "arith_operand" "dI")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
 
@@ -7328,7 +7331,7 @@
 	       (match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -7374,7 +7377,7 @@
 	       (match_operand:SI 2 "arith_operand" "dI")))]
   "!TARGET_MIPS16"
   "slt\t%0,%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn ""
@@ -7383,7 +7386,7 @@
 	       (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_MIPS16"
   "slt\t%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -7397,7 +7400,7 @@
 	       (match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "slt\t%0,%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -7406,7 +7409,7 @@
 	       (match_operand:DI 2 "arith_operand" "d,I")))]
   "TARGET_64BIT && TARGET_MIPS16"
   "slt\t%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -7448,7 +7451,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
   return "slt\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn ""
@@ -7460,7 +7463,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
   return "slt\t%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
 				      (const_int 4)
@@ -7475,7 +7478,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
   return "slt\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -7487,7 +7490,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
   return "slt\t%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
 				      (const_int 4)
@@ -7499,7 +7502,7 @@
 	       (match_operand:SI 2 "register_operand" "d")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
 
@@ -7522,7 +7525,7 @@
 	       (match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -7571,7 +7574,7 @@
 		(match_operand:SI 2 "reg_or_0_operand" "dJ")))]
   "!TARGET_MIPS16"
   "sltu\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn ""
@@ -7580,7 +7583,7 @@
 		(match_operand:SI 2 "register_operand" "d")))]
   "TARGET_MIPS16"
   "sltu\t%2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn "sgtu_di"
@@ -7589,7 +7592,7 @@
 		(match_operand:DI 2 "reg_or_0_operand" "dJ")))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "sltu\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -7598,7 +7601,7 @@
 		(match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_MIPS16"
   "sltu\t%2,%1"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_expand "sgeu"
@@ -7629,7 +7632,7 @@
 		(match_operand:SI 2 "arith_operand" "dI")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
 
@@ -7652,7 +7655,7 @@
 		(match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -7698,7 +7701,7 @@
 		(match_operand:SI 2 "arith_operand" "dI")))]
   "!TARGET_MIPS16"
   "sltu\t%0,%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn ""
@@ -7707,7 +7710,7 @@
 		(match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_MIPS16"
   "sltu\t%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -7721,7 +7724,7 @@
 		(match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "sltu\t%0,%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -7730,7 +7733,7 @@
 		(match_operand:DI 2 "arith_operand" "d,I")))]
   "TARGET_64BIT && TARGET_MIPS16"
   "sltu\t%1,%2"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
 		[(const_int 4)
@@ -7772,7 +7775,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
   return "sltu\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")])
 
 (define_insn ""
@@ -7784,7 +7787,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
   return "sltu\t%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"SI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
 				      (const_int 4)
@@ -7799,7 +7802,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
   return "sltu\t%0,%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")])
 
 (define_insn ""
@@ -7811,7 +7814,7 @@
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
   return "sltu\t%1,%2";
 }
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"slt")
    (set_attr "mode"	"DI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
 				      (const_int 4)
@@ -7823,7 +7826,7 @@
 		(match_operand:SI 2 "register_operand" "d")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
 
@@ -7846,7 +7849,7 @@
 		(match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
+  [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
 
@@ -8864,7 +8867,7 @@
     else
       return "#nop";
   }
-  [(set_attr "type"	"arith")])
+  [(set_attr "type"	"nop")])
 
 ;; MIPS4 Conditional move instructions.
 
Index: sr71k.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/sr71k.md,v
retrieving revision 1.6
diff -u -r1.6 sr71k.md
--- sr71k.md	16 Mar 2004 02:11:41 -0000	1.6
+++ sr71k.md	17 Mar 2004 02:15:41 -0000
@@ -201,7 +201,7 @@
 (define_insn_reservation "ir_sr70_arith"
                                1
                           (and (eq_attr "cpu" "sr71000")
-                               (eq_attr "type" "move,arith,darith,const"))
+                               (eq_attr "type" "move,arith,shift,slt,clz,const"))
                          "ri_insns")
 
 ;; emulate repeat (dispatch stall) by spending extra cycle(s) in

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