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Re: [PATCH]: Use define_insn_and_split in 68HC11 port



Oops... the patch attached...


Stephane
Index: config/m68hc11/m68hc11.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11.md,v
retrieving revision 1.54.10.1
diff -u -p -r1.54.10.1 m68hc11.md
--- config/m68hc11/m68hc11.md	2 Mar 2004 21:01:12 -0000	1.54.10.1
+++ config/m68hc11/m68hc11.md	2 Mar 2004 21:13:11 -0000
@@ -249,19 +249,13 @@
 ;; avoid problems with the flow+cse register pass which are made
 ;; after Z register replacement.
 ;;
-(define_insn "tstqi_z_used"
+(define_insn_and_split "tstqi_z_used"
   [(set (cc0)
 	(match_operand:QI 0 "tst_operand" "m"))
    (use (match_operand:HI 1 "hard_reg_operand" "dxy"))
    (use (reg:HI SOFT_Z_REGNUM))]
   ""
-  "#")
-
-(define_split /* "tstqi_z_used" */
-  [(set (cc0)
-	(match_operand:QI 0 "tst_operand" ""))
-   (use (match_operand:HI 1 "hard_reg_operand" ""))
-   (use (reg:HI SOFT_Z_REGNUM))]
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
    (set (match_dup 1) (match_dup 2))
@@ -302,12 +296,24 @@
   [(set (cc0)
 	(compare (match_operand:HI 0 "hard_reg_operand" "")
 		 (match_operand:HI 1 "hard_reg_operand" "")))]
-  "reload_completed"
+  "TARGET_M6811
+   && reload_completed && !(Z_REG_P (operands[0]) || Z_REG_P (operands[1]))"
   [(set (match_dup 2) (match_dup 1))
    (set (cc0)
         (compare (match_dup 0) (match_dup 2)))]
   "operands[2] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM);")
 
+(define_split
+  [(set (cc0)
+	(compare (match_operand:HI 0 "hard_reg_operand" "")
+		 (match_operand:HI 1 "hard_reg_operand" "")))]
+  "TARGET_M6812
+   && reload_completed && !(Z_REG_P (operands[0]) || Z_REG_P (operands[1]))"
+  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
+   (set (cc0)
+        (compare (match_dup 0) (mem:HI (post_inc:HI (reg:HI SP_REGNUM)))))]
+  "")
+
 (define_expand "cmphi"
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" "")
@@ -327,7 +333,7 @@
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" 
 				"d,?xy,xyd,?xy,d,m,!u,dxy,dxy")
-		 (match_operand:HI 1 "cmp_operand"
+		 (match_operand:HI 1 "general_operand"
 				"i,i,!u,m,m,dxy,dxy,?*d*A,!*w")))]
   "TARGET_M6812"
   "*
@@ -346,9 +352,9 @@
 (define_insn "cmphi_1_hc11"
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" 
-				"dx,y,xyd,?xy,d,m,!u,dxy,dxy")
+				"dx,y,xyd,?xy,d,m,m,dxy,dxy,?u*z,dxy,*z")
 		 (match_operand:HI 1 "cmp_operand"
-				"i,i,!u,m,m,dxy,dxy,?*d*A,!*w")))]
+				"i,i,!u,m,m,?xy,d,?*d*A,?u,dxy,!*w,i")))]
   "TARGET_M6811"
   "*
 {
@@ -363,21 +369,14 @@
     return \"cp%0\\t%1\";
 }")
 
-(define_insn "cmphi_z_used"
+(define_insn_and_split "cmphi_z_used"
   [(set (cc0)
 	(compare (match_operand:HI 0 "tst_operand" "dxy,m")
-		 (match_operand:HI 1 "cmp_operand" "m,dxy")))
+		 (match_operand:HI 1 "cmp_operand" "mi,dxy")))
    (use (match_operand:HI 2 "hard_reg_operand" "dxy,dxy"))
    (use (reg:HI SOFT_Z_REGNUM))]
   ""
-  "#")
-  
-(define_split /* "cmphi_z_used" */
-  [(set (cc0)
-	(compare (match_operand:HI 0 "tst_operand" "")
-		 (match_operand:HI 1 "cmp_operand" "")))
-   (use (match_operand:HI 2 "hard_reg_operand" ""))
-   (use (reg:HI SOFT_Z_REGNUM))]
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))
    (set (match_dup 2) (match_dup 3))
@@ -454,21 +453,14 @@
    operands[3] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM);
    operands[4] = gen_rtx (REG, QImode, SOFT_TMP_REGNUM);")
 
-(define_insn "bitcmpqi_z_used"
+(define_insn_and_split "bitcmpqi_z_used"
   [(set (cc0)
 	(and:QI (match_operand:QI 0 "tst_operand" "d,m")
 		(match_operand:QI 1 "cmp_operand" "m,d")))
    (use (match_operand:HI 2 "hard_reg_operand" "xy,xy"))
    (use (reg:HI SOFT_Z_REGNUM))]
   ""
-  "#")
-  
-(define_split /* "bitcmpqi_z_used" */
-  [(set (cc0)
-	(and:QI (match_operand:QI 0 "tst_operand" "")
-		(match_operand:QI 1 "cmp_operand" "")))
-   (use (match_operand:HI 2 "hard_reg_operand" ""))
-   (use (reg:HI SOFT_Z_REGNUM))]
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))
    (set (match_dup 2) (match_dup 3))
@@ -544,21 +536,14 @@
    return \"cmpb\\t%b0\";
 }")
 
-(define_insn "cmpqi_z_used"
+(define_insn_and_split "cmpqi_z_used"
   [(set (cc0)
 	(compare (match_operand:QI 0 "tst_operand" "dxy,m")
 		 (match_operand:QI 1 "cmp_operand" "m,dxy")))
    (use (match_operand:HI 2 "hard_reg_operand" "dxy,dxy"))
    (use (reg:HI SOFT_Z_REGNUM))]
   ""
-  "#")
-  
-(define_split /* cmpqi_z_used */
-  [(set (cc0)
-	(compare (match_operand:QI 0 "tst_operand" "")
-		 (match_operand:QI 1 "cmp_operand" "")))
-   (use (match_operand:HI 2 "hard_reg_operand" ""))
-   (use (reg:HI SOFT_Z_REGNUM))]
+  "#"
   "z_replacement_completed == 2"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))
    (set (match_dup 2) (match_dup 3))
@@ -575,41 +560,29 @@
 ;; (strict_low_part ...) information.  This is correct for our machine
 ;; description but not for GCC optimization passes.
 ;;
-(define_insn "movstrictsi"
+(define_insn_and_split "movstrictsi"
   [(set (strict_low_part (match_operand:SI 0 "non_push_operand" "+um,D,D"))
 	(match_operand:SI 1 "general_operand" "D,Dim,uD"))]
   ""
-  "#")
-
-(define_split
-  [(set (strict_low_part (match_operand:SI 0 "non_push_operand" ""))
-	(match_operand:SI 1 "general_operand" ""))]
+  "#"
   "z_replacement_completed == 2"
   [(set (match_dup 0) (match_dup 1))]
   "")
 
-(define_insn "movstricthi"
+(define_insn_and_split "movstricthi"
   [(set (strict_low_part (match_operand:HI 0 "non_push_operand" "+um,dA,dA"))
 	(match_operand:HI 1 "general_operand" "dA,dAim,u"))]
   ""
-  "#")
-
-(define_split
-  [(set (strict_low_part (match_operand:HI 0 "non_push_operand" ""))
-	(match_operand:HI 1 "general_operand" ""))]
+  "#"
   "z_replacement_completed == 2"
   [(set (match_dup 0) (match_dup 1))]
   "")
 
-(define_insn "movstrictqi"
+(define_insn_and_split "movstrictqi"
   [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,!dA"))
 	(match_operand:QI 1 "general_operand" "d,imudA"))]
   ""
-  "#")
-
-(define_split
-  [(set (strict_low_part (match_operand:QI 0 "non_push_operand" ""))
-	(match_operand:QI 1 "general_operand" ""))]
+  "#"
   "z_replacement_completed == 2"
   [(set (match_dup 0) (match_dup 1))]
   "")
@@ -3056,21 +3029,29 @@
 ;;- and instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "anddi3"
+(define_insn_and_split "anddi3"
   [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
 	(and:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
 		(match_operand:DI 2 "general_operand" "imu,imu")))
    (clobber (match_scratch:HI 3 "=d,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (SImode, AND, operands);
+   DONE;")
 
-(define_insn "andsi3"
+(define_insn_and_split "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=D,!u")
 	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
 		(match_operand:SI 2 "general_operand" "Dimu,imu")))
    (clobber (match_scratch:HI 3 "=X,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (HImode, AND, operands);
+   DONE;")
 
 (define_expand "andhi3"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -3332,21 +3313,29 @@
 ;;- Bit set or instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "iordi3"
+(define_insn_and_split "iordi3"
   [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
 	(ior:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
 		(match_operand:DI 2 "general_operand" "imu,imu")))
    (clobber (match_scratch:HI 3 "=d,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (SImode, IOR, operands);
+   DONE;")
 
-(define_insn "iorsi3"
+(define_insn_and_split "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "=D,!u")
 	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
 		(match_operand:SI 2 "general_operand" "Dimu,imu")))
    (clobber (match_scratch:HI 3 "=X,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (HImode, IOR, operands);
+   DONE;")
 
 (define_expand "iorhi3"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -3543,21 +3532,29 @@
 ;;- xor instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "xordi3"
+(define_insn_and_split "xordi3"
   [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
 	(xor:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
 		(match_operand:DI 2 "general_operand" "imu,imu")))
    (clobber (match_scratch:HI 3 "=d,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (SImode, XOR, operands);
+   DONE;")
 
-(define_insn "xorsi3"
+(define_insn_and_split "xorsi3"
   [(set (match_operand:SI 0 "register_operand" "=D,!u")
 	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
 		(match_operand:SI 2 "general_operand" "Dimu,imu")))
    (clobber (match_scratch:HI 3 "=X,d"))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+  "m68hc11_split_logical (HImode, XOR, operands);
+   DONE;")
 
 (define_insn "xorhi3"
   [(set (match_operand:HI 0 "register_operand" "=d,d,!*A")
@@ -3643,30 +3640,47 @@
 ;;- Bit set or instructions.
 ;;--------------------------------------------------------------------
 
-(define_insn "*logicalsi3_zexthi"
+(define_insn_and_split "*logicalsi3_zexthi"
   [(set (match_operand:SI 0 "register_operand" "=D")
 	(match_operator:SI 3 "m68hc11_logical_operator"
 		[(zero_extend:SI
 		     (match_operand:HI 1 "general_operand" "imudA"))
 		 (match_operand:SI 2 "general_operand" "Dimu")]))]
   ""
-  "#")
+  "#"
+  "reload_completed"
+  [(set (reg:HI D_REGNUM) (match_dup 4))
+   (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)]))
+   (set (reg:HI X_REGNUM) (match_dup 6))]
+  "PUT_MODE (operands[3], HImode);
+   if (X_REG_P (operands[2]))
+     {
+       operands[5] = operands[1];
+       /* Make all the (set (REG:x) (REG:y)) a nop set.  */
+       operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
+       operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
+     }
+   else
+     {
+       operands[4] = operands[1];
+       operands[5] = m68hc11_gen_lowpart (HImode, operands[2]);
+       operands[6] = m68hc11_gen_highpart (HImode, operands[2]);
+     }
+   /* For an AND, make sure the high 16-bit part is cleared.  */
+   if (GET_CODE (operands[3]) == AND)
+     {
+       operands[6] = const0_rtx;
+     }
+   ")
 
-(define_insn "*logicalsi3_zextqi"
+(define_insn_and_split "*logicalsi3_zextqi"
   [(set (match_operand:SI 0 "register_operand" "=D,D,D")
 	(match_operator:SI 3 "m68hc11_logical_operator"
 		[(zero_extend:SI
 		     (match_operand:QI 1 "general_operand" "d,*A,imu"))
 		 (match_operand:SI 2 "general_operand" "imu,imu,0")]))]
   ""
-  "#")
-
-(define_split /* logicalsi3_zextqi */
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operator:SI 3 "m68hc11_logical_operator"
-	         [(zero_extend:SI
-		     (match_operand:QI 1 "general_operand" ""))
-		  (match_operand:SI 2 "general_operand" "")]))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:QI A_REGNUM) (match_dup 4))
    (set (reg:QI D_REGNUM) (match_dup 7))
@@ -3697,63 +3711,47 @@
      }
    ")
 
-(define_split /* logicalsi3_zexthi */
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operator:SI 3 "m68hc11_logical_operator"
-	         [(zero_extend:SI
-		     (match_operand:HI 1 "general_operand" ""))
-		  (match_operand:SI 2 "general_operand" "")]))]
-  "reload_completed"
-  [(set (reg:HI D_REGNUM) (match_dup 4))
-   (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)]))
-   (set (reg:HI X_REGNUM) (match_dup 6))]
-  "PUT_MODE (operands[3], HImode);
-   if (X_REG_P (operands[2]))
-     {
-       operands[5] = operands[1];
-       /* Make all the (set (REG:x) (REG:y)) a nop set.  */
-       operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
-       operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
-     }
-   else
-     {
-       operands[4] = operands[1];
-       operands[5] = m68hc11_gen_lowpart (HImode, operands[2]);
-       operands[6] = m68hc11_gen_highpart (HImode, operands[2]);
-     }
-   /* For an AND, make sure the high 16-bit part is cleared.  */
-   if (GET_CODE (operands[3]) == AND)
-     {
-       operands[6] = const0_rtx;
-     }
-   ")
-
-(define_insn "*logicalhi3_zexthi_ashift8"
+(define_insn_and_split "*logicalhi3_zexthi_ashift8"
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(match_operator:HI 3 "m68hc11_logical_operator"
 		[(zero_extend:HI
-		     (match_operand:QI 1 "general_operand" "imud"))
+		     (match_operand:QI 1 "general_operand" "imud*A"))
 		 (ashift:HI
-		     (match_operand:HI 2 "general_operand" "dimu")
+		     (match_operand:HI 2 "general_operand" "imud*A")
 		     (const_int 8))]))]
   ""
-  "#")
+  "#"
+  "z_replacement_completed == 2"
+  [(set (reg:QI A_REGNUM) (match_dup 4))
+   (set (reg:QI B_REGNUM) (match_dup 5))]
+  "
+   if (GET_CODE (operands[3]) == AND)
+     {
+       emit_insn (gen_movhi (operands[0], const0_rtx));
+       DONE;
+     }
+   else
+     {
+       operands[5] = operands[1];
+       if (D_REG_P (operands[2]))
+         {
+           operands[4] = gen_rtx (REG, QImode, HARD_B_REGNUM);
+         }
+       else
+         {
+           operands[4] = m68hc11_gen_lowpart (QImode, operands[2]);
+         }
+     }
+  ")
 
-(define_insn "*logicalhi3_zexthi"
+(define_insn_and_split "*logicalhi3_zexthi"
   [(set (match_operand:HI 0 "register_operand" "=d,d")
 	(match_operator:HI 3 "m68hc11_logical_operator"
 		[(zero_extend:HI
 		     (match_operand:QI 1 "general_operand" "imd*A,?u"))
 		 (match_operand:HI 2 "general_operand" "dim,?dimu")]))]
   ""
-  "#")
-
-(define_split /* logicalhi3_zexthi */
-  [(set (match_operand:HI 0 "register_operand" "")
-	(match_operator:HI 3 "m68hc11_logical_operator"
-		[(zero_extend:HI
-		     (match_operand:QI 1 "general_operand" ""))
-		 (match_operand:HI 2 "general_operand" "")]))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:QI B_REGNUM) (match_dup 6))
    (set (reg:QI A_REGNUM) (match_dup 4))
@@ -3782,54 +3780,16 @@
      }
   ")
 
-(define_split /* logicalhi3_zexthi_ashift8 */
-  [(set (match_operand:HI 0 "register_operand" "")
-	(match_operator:HI 3 "m68hc11_logical_operator"
-		[(zero_extend:HI
-		     (match_operand:QI 1 "general_operand" ""))
-		 (ashift:HI
-		     (match_operand:HI 2 "general_operand" "")
-		     (const_int 8))]))]
-  "z_replacement_completed == 2"
-  [(set (reg:QI A_REGNUM) (match_dup 4))
-   (set (reg:QI B_REGNUM) (match_dup 5))]
-  "
-   if (GET_CODE (operands[3]) == AND)
-     {
-       emit_insn (gen_movhi (operands[0], const0_rtx));
-       DONE;
-     }
-   else
-     {
-       operands[5] = operands[1];
-       if (D_REG_P (operands[2]))
-         {
-           operands[4] = gen_rtx (REG, QImode, HARD_B_REGNUM);
-         }
-       else
-         {
-           operands[4] = m68hc11_gen_lowpart (QImode, operands[2]);
-         }
-     }
-  ")
 
-(define_insn "*logicalsi3_silshr16"
-  [(set (match_operand:SI 0 "register_operand" "=D,D,D")
+(define_insn_and_split "*logicalsi3_silshr16"
+  [(set (match_operand:SI 0 "register_operand" "=D,D,D,?D")
           (match_operator:SI 3 "m68hc11_logical_operator"
 	      [(lshiftrt:SI 
-		   (match_operand:SI 1 "general_operand" "uim,uim,?D")
+		   (match_operand:SI 1 "general_operand" "uim,uim,0,0")
 		   (const_int 16))
-		(match_operand:SI 2 "general_operand" "uim,0,0")]))]
+		(match_operand:SI 2 "general_operand" "uim,0,uim,0")]))]
   ""
-  "#")
-
-(define_split /* logicalsi3_silshr16 */
-  [(set (match_operand:SI 0 "register_operand" "")
-          (match_operator:SI 3 "m68hc11_logical_operator"
-		[(lshiftrt:SI 
-			(match_operand:SI 1 "general_operand" "")
-			(const_int 16))
-		 (match_operand:SI 2 "general_operand" "")]))]
+  "#"
   "reload_completed"
   [(set (reg:HI D_REGNUM) (match_dup 4))
    (set (reg:HI D_REGNUM) (match_op_dup 3 [(reg:HI D_REGNUM) (match_dup 5)]))
@@ -3854,7 +3814,7 @@
      }
 ")
 
-(define_insn "*logicalsi3_silshl16"
+(define_insn_and_split "*logicalsi3_silshl16"
   [(set (match_operand:SI 0 "register_operand" "=D,D")
           (match_operator:SI 3 "m68hc11_logical_operator"
 	      [(ashift:SI 
@@ -3862,15 +3822,7 @@
 		   (const_int 16))
 		(match_operand:SI 2 "general_operand" "0,0")]))]
   ""
-  "#")
-
-(define_split /* logicalsi3_silshl16 */
-  [(set (match_operand:SI 0 "register_operand" "")
-          (match_operator:SI 3 "m68hc11_logical_operator"
-		[(ashift:SI 
-			(match_operand:SI 1 "general_operand" "")
-			(const_int 16))
-		 (match_operand:SI 2 "general_operand" "")]))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:HI X_REGNUM) (match_op_dup 3 [(reg:HI X_REGNUM) (match_dup 4)]))
    (set (reg:HI D_REGNUM) (match_dup 5))]
@@ -3883,48 +3835,45 @@
      operands[5] = gen_rtx (REG, HImode, HARD_D_REGNUM);
    ")
 
-
-;;--------------------------------------------------------------------
-;;- 64/32-bit Logical Operations.  Patterns are defined so that GCC
-;; can optimize correctly.  These insns are split by the `final'
-;; pass (# pattern).  They are split to fall in the corresponding
-;; 16-bit logical patterns.
-;;--------------------------------------------------------------------
-
-;; Split 64-bit logical operations: anddi3, iordi3, xordi3
-(define_split
-  [(set (match_operand:DI 0 "reg_or_some_mem_operand" "")
-	(match_operator:DI 4 "m68hc11_logical_operator"
-	     [(match_operand:DI 1 "reg_or_some_mem_operand" "")
-	      (match_operand:DI 2 "general_operand" "")]))
-   (clobber (match_scratch:HI 3 ""))]
+(define_insn_and_split "*logicalsi3_silshl16_zext"
+  [(set (match_operand:SI 0 "register_operand" "=D,D,D")
+          (match_operator:SI 3 "m68hc11_logical_operator"
+	      [(ashift:SI
+	          (zero_extend:SI
+		     (match_operand:HI 1 "general_operand" "uim,udA,!dA"))
+		  (const_int 16))
+	    (zero_extend:SI (match_operand:HI 2 "general_operand" "uidA,um,!dA"))]))]
+  ""
+  "#"
+  ;; Must split before z register replacement
   "reload_completed"
-  [(const_int 0)]
-  "m68hc11_split_logical (SImode, GET_CODE (operands[4]), operands);
-   DONE;")
-
-;; Split 32-bit logical operations: andsi3, iorsi3, xorsi3
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operator:SI 3 "m68hc11_logical_operator"
-	     [(match_operand:SI 1 "register_operand" "")
-	      (match_operand:SI 2 "general_operand" "")]))]
-  "0 && reload_completed"
-  [(const_int 0)]
-  "m68hc11_split_logical (HImode, GET_CODE (operands[3]), operands);
-   DONE;")
+  [(set (match_dup 4) (match_dup 5))
+   (set (match_dup 6) (match_dup 7))]
+  "
+    /* set (X_REGNUM) (d), set (D_REGNUM) (1) */
+   if (GET_CODE (operands[1]) == HARD_D_REGNUM
+       && GET_CODE (operands[3]) != AND)
+     {
+       /* This particular case is too early to be split before
+          Z register replacement because the cse-reg pass we do
+	  does not recognize the 'swap_areg'.  It is ok to handle
+	  this case after.  */
+       if (z_replacement_completed != 2)
+         {
+	   FAIL;
+	 }
+       emit_move_insn (gen_rtx (REG, HImode, HARD_X_REGNUM), operands[2]);
+       emit_insn (gen_swap_areg (gen_rtx (REG, HImode, HARD_D_REGNUM),
+			         gen_rtx (REG, HImode, HARD_X_REGNUM)));
+     }
+   operands[4] = gen_rtx (REG, HImode, HARD_D_REGNUM);
+   operands[6] = gen_rtx (REG, HImode, HARD_X_REGNUM);
+   operands[5] = operands[2];
+   operands[7] = operands[1];
 
-;; Split 32-bit logical operations: andsi3, iorsi3, xorsi3
-(define_split
-  [(set (match_operand:SI 0 "reg_or_some_mem_operand" "")
-	(match_operator:SI 4 "m68hc11_logical_operator"
-	     [(match_operand:SI 1 "reg_or_some_mem_operand" "")
-	      (match_operand:SI 2 "general_operand" "")]))
-   (clobber (match_scratch:HI 3 ""))]
-  "reload_completed"
-  [(const_int 0)]
-  "m68hc11_split_logical (HImode, GET_CODE (operands[4]), operands);
-   DONE;")
+   if (GET_CODE (operands[3]) == AND)
+     operands[5] = operands[7] = const0_rtx;
+   ")
 
 ;;--------------------------------------------------------------------
 ;; 16-bit Arithmetic and logical operations on X and Y:
@@ -4423,19 +4372,13 @@
     }
 }")
 
-(define_insn "*ashldi3_const32"
+(define_insn_and_split "*ashldi3_const32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u")
 	(ashift:DI (match_operand:DI 1 "general_operand" "umi,umi,umi")
 		   (const_int 32)))
    (clobber (match_scratch:HI 2 "=&A,d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(ashift:DI (match_operand:DI 1 "general_operand" "")
-		   (const_int 32)))
-   (clobber (match_scratch:HI 2 ""))]
+   "#"
    "reload_completed"
    [(const_int 0)]
    "/* Move the lowpart in the highpart first in case the shift
@@ -4462,19 +4405,13 @@
       }
     DONE;")
 
-(define_insn "*ashldi3_const1"
+(define_insn_and_split "*ashldi3_const1"
   [(set (match_operand:DI 0 "non_push_operand" "=m,m,u")
 	(ashift:DI (match_operand:DI 1 "general_operand" "mi,u,umi")
 		   (const_int 1)))
    (clobber (match_scratch:HI 2 "=d,d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "non_push_operand" "")
-	(ashift:DI (match_operand:DI 1 "general_operand" "")
-		   (const_int 1)))
-   (clobber (match_scratch:HI 2 ""))]
+   "#"
    "z_replacement_completed == 2"
    [(set (match_dup 2) (match_dup 3))
     (set (match_dup 2) (ashift:HI (match_dup 2) (const_int 1)))
@@ -4514,10 +4451,10 @@
     operands[8] = m68hc11_gen_lowpart (HImode, operands[8]);")
 
 (define_insn "addsi_silshr16"
-  [(set (match_operand:SI 0 "register_operand" "=D,D")
-          (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "!*uim,0")
+  [(set (match_operand:SI 0 "register_operand" "=D,D,!D")
+          (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "!*uim,0,0")
 				(const_int 16))
-		   (match_operand:SI 2 "general_operand" "0,m!*u")))]
+		   (match_operand:SI 2 "general_operand" "0,m!*u,0")))]
   ""
   "#")
 
@@ -4582,19 +4519,13 @@
   operands[4] = m68hc11_gen_lowpart (HImode, operands[2]);
 }")
 
-(define_insn "addsi_andshr16"
+(define_insn_and_split "addsi_andshr16"
   [(set (match_operand:SI 0 "register_operand" "=D")
           (plus:SI (and:SI (match_operand:SI 1 "general_operand" "%uim")
 			   (const_int 65535))
 		   (match_operand:SI 2 "general_operand" "0")))]
   ""
-  "#")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-          (plus:SI (and:SI (match_operand:SI 1 "general_operand" "")
-			   (const_int 65535))
-		   (match_operand:SI 2 "general_operand" "")))]
+  "#"
   "z_replacement_completed == 2"
   [(set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 3)))
    (set (reg:HI X_REGNUM) (plus:HI (plus:HI (reg:HI X_REGNUM) (const_int 0)) (reg:HI CC_REGNUM)))]
@@ -4641,21 +4572,14 @@
    ""
    "#")
 
-(define_insn "*ashlsi3_const16_zexthi"
+(define_insn_and_split "*ashlsi3_const16_zexthi"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=D")
 	(ashift:SI (zero_extend:HI 
 			(match_operand:HI 1 "general_operand" "duim*A"))
 	           (const_int 16)))
    (clobber (match_scratch:HI 2 "=X"))]
    ""
-   "#")
-
-(define_split /* "*ashlsi3_const16_zexthi"*/
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(ashift:SI (zero_extend:HI 
-			(match_operand:HI 1 "general_operand" ""))
-	           (const_int 16)))
-   (clobber (match_scratch:HI 2 "=X"))]
+   "#"
    "reload_completed"
    [(set (reg:HI X_REGNUM) (match_dup 1))
     (set (reg:HI D_REGNUM) (const_int 0))]
@@ -5259,19 +5183,13 @@
     }
 }")
 
-(define_insn "*lshrdi3_const32"
+(define_insn_and_split "*lshrdi3_const32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi,umi")
 		     (const_int 32)))
    (clobber (match_scratch:HI 2 "=&A,d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
-		     (const_int 32)))
-   (clobber (match_scratch:HI 2 "=&A,d"))]
+   "#"
    "reload_completed"
    [(const_int 0)]
    "m68hc11_split_move (m68hc11_gen_lowpart (SImode, operands[0]),
@@ -5341,19 +5259,13 @@
     operands[7] = m68hc11_gen_highpart (HImode, operands[6]);
     operands[6] = m68hc11_gen_lowpart (HImode, operands[6]);")
 
-(define_insn "*lshrdi_const1"
+(define_insn_and_split "*lshrdi_const1"
   [(set (match_operand:DI 0 "non_push_operand" "=m,u")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi")
 		     (const_int 1)))
    (clobber (match_scratch:HI 2 "=d,d"))]
    ""
-   "#")
-
-(define_split
-  [(set (match_operand:DI 0 "non_push_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
-		     (const_int 1)))
-   (clobber (match_scratch:HI 2 ""))]
+   "#"
    "z_replacement_completed == 2"
    [(set (match_dup 2) (match_dup 3))
     (set (match_dup 2) (lshiftrt:HI (match_dup 2) (const_int 1)))

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