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Re: PATCH:[darwin] fix load of a misaligned double word
- From: "Hartmut Penner" <HPENNER at de dot ibm dot com>
- To: Bradley Lucier <lucier at math dot purdue dot edu>
- Cc: David Edelsohn <dje at makai dot watson dot ibm dot com>, fjahanian at apple dot com, gcc-patches at gcc dot gnu dot org, Geoff Keating <geoffk at geoffk dot org>, Bradley Lucier <lucier at math dot purdue dot edu>, pinskia at physics dot uc dot edu, "Ulrich Weigand" <Ulrich dot Weigand at de dot ibm dot com>
- Date: Wed, 21 Jan 2004 09:30:26 +0100
- Subject: Re: PATCH:[darwin] fix load of a misaligned double word
> I was thinking that the proper way to test this patch is to bootstrap
> and regression test with BOOT_CFLAGS='-O2 -g -mcpu=G5' with and without
> the patch. But I can't bootstrap 3.4 branch or mainline with or
> without this patch, so ...
Did test it on mainline for PPC64 linux, but I agree, we need also
a test on Darwin.
> I filed a proper bug report at
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13778
> I can't get the patch to apply cleanly to either mainline or 3.4
> branch, either. I can't tell what I'm doing wrong ...
> Brad
Append a cleanly build patch for mainline.
ChangeLog
2004-01-21 Hartmut Penner <hpenner@de.ibm.com>
PR target/13778
* gcc/config/rs6000/rs6000.c (secondary_reload_class)
Allocate BASE_REG for reload_{in|out}df
* gcc/config/rs6000/rs6000.md (reload_outdf) New.
(reload_indf) New.
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.581
diff -u -p -r1.581 rs6000.c
--- config/rs6000/rs6000.c 20 Jan 2004 16:51:07 -0000 1.581
+++ config/rs6000/rs6000.c 21 Jan 2004 08:22:27 -0000
@@ -8403,6 +8403,16 @@ secondary_reload_class (enum reg_class c
else
regno = -1;
+ /* Invalid 'Y' addresses in movdf insn need secondary reload. */
+ if (TARGET_POWERPC64
+ && mode == DFmode
+ && reg_classes_intersect_p (GENERAL_REGS, class)
+ && GET_CODE (in) == MEM
+ && !word_offset_memref_operand (in, mode))
+ {
+ return BASE_REGS;
+ }
+
/* We can place anything into GENERAL_REGS and can put GENERAL_REGS
into anything. */
if (class == GENERAL_REGS || class == BASE_REGS
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.284
diff -u -p -r1.284 rs6000.md
--- config/rs6000/rs6000.md 12 Jan 2004 18:37:40 -0000 1.284
+++ config/rs6000/rs6000.md 21 Jan 2004 08:22:33 -0000
@@ -8163,7 +8163,7 @@
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*movdf_hardfloat64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,??r,!r,f,f,m,!cl,!r,!r,!r,!r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=?Y,?r,!r,f,f,m,!cl,!r,!r,!r,!r")
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,G,H,F"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DFmode)
@@ -8201,6 +8201,43 @@
nop"
[(set_attr "type" "load,store,*,*,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,8,12,16,4")])
+
+/* Secondary reload, for reloads of movdf insn,
+ if address does not satisfy the 'Y' constraint.
+*/
+
+(define_expand "reload_outdf"
+ [(parallel [(match_operand:DF 0 "memory_operand" "")
+ (match_operand:DF 1 "register_operand" "")
+ (match_operand:DI 2 "register_operand" "=&b")])]
+ "TARGET_POWERPC64"
+{
+ if (TARGET_64BIT)
+ emit_move_insn (operands[2], XEXP (operands[0], 0));
+ else
+ emit_move_insn (gen_lowpart_SUBREG (SImode, operands[2]),
+ XEXP (operands[0], 0));
+ operands[0] = replace_equiv_address (operands[0], operands[2]);
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
+(define_expand "reload_indf"
+ [(parallel [(match_operand:DF 0 "register_operand" "")
+ (match_operand:DF 1 "memory_operand" "")
+ (match_operand:DI 2 "register_operand" "=&b")])]
+ "TARGET_POWERPC64"
+{
+ if (TARGET_64BIT)
+ emit_move_insn (operands[2], XEXP (operands[1], 0));
+ else
+ emit_move_insn (gen_lowpart_SUBREG (SImode, operands[2]),
+ XEXP (operands[1], 0));
+ operands[1] = replace_equiv_address (operands[1], operands[2]);
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")