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Re: PR gcc/7618: Support MI thunks in the MIPS backend

Ian Lance Taylor <> writes:
> Here is a sample patch to add support for MI thunks to the MIPS
> backend.  This is for PR gcc/7618.

To be honest, I've been very reluctant to do this.  Two main reasons:

- As your patch demonstrates, there's not really any special
  MIPS-specific tricks that we can pull.  It's really just a case
  of using standard patterns.

  I was hoping that (at least after tree-ssa) it would be possible
  to provide a target-independent implementation.

- It's always difficult writing out MIPS asm directly.  There are so
  many variations to worry about.  (At least 6 ABI variations that
  I think of as supported, plus PIC/no-PIC and mips16/non-mips16.)

  The necessary logic is already present elsewhere in the compiler,
  but it's all geared towards rtl.  If we're trying to write out
  the asm directly, we end up having to duplicate a lot of it.

Plus a minor reason: when using explicit relocs for -mabicalls,
I suspect the current (generic) implementation will give slightly
better code for the cases that it can handle.

WRT patch itself:

- I couldn't see any code to set up the gp for TARGET_ABICALLS.
  Note that you'll need to use a call-clobbered register rather
  than $gp for TARGET_NEWABI.

- The mips16 call sequence looks wrong.  "la" and "dla" can only be used
  for (PC-relative) references to constant pool labels.  You can't use
  them for loading arbitrary addresses.

- Did you consider using an rtl implementation, like alpha or rs6000?


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