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Re: [PATCH] Reload CONST_VECTOR into memory on ppc.


"Geoff Keating" <geoffk@geoffk.org> writes:
> I have one concern:

> > @@ -1718,17 +1736,31 @@ output_vec_const_move (rtx *operands)
> >      {
> >        if (zero_constant (vec, mode))
> >       return "vxor %0,%0,%0";
> > -      else if (EASY_VECTOR_15 (cst, vec, mode))
> > +      else if (easy_vector_constant (vec, mode))

> This change will cause an abort() when EASY_VECTOR_15_ADD_SELF is true.

Yes, fixed by testing EASY_VECTOR_15_ADD_SELF befor easy_vector_constant
(see patch below)

> I think this patch does need a testcase.  I would suggest something like:

> extern void foo (vector int);

> void bar(void) {
> foo ((vector int) { 1,1,1,1 });
> foo ((vector int) { 0x10001,0x10001,0x10001,0x10001 });
> foo ((vector int) { 0x1010101, 0x1010101, 0x1010101, 0x1010101 });
> ...
> }

> and so on, testing both positive and negative values; then you should
> be able to just scan the assembler for any vector load or store
> operations using dg-scan-assembler-not, since this shouldn't generate
any.

Did write it as altivec-11.c. Will test for zero vector,
easy_vector_15_add_self
and easy_vector_constant exploitation. Already found with this testcase a
bug in my patch ...

Compiled and tested on powerpc64-linux (also tested with -m32 for
powerpc-linux).
OK to commit ?


Changelog gcc:

2004-01-07  Hartmut Penner  <hpenner@de.ibm.com>

      * gcc/config/rs6000/rs6000.c (easy_vector_constant): Accept
      all vector constant loadable by vsplt*.
      (output_vec_const_move): Likewise.

Changelog gcc/testsuite:

2004-01-07  Hartmut Penner  <hpenner@de.ibm.com>

      * gcc.dg/altivec-11.c: New test.


Index: gcc/config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.566
diff -u -p -r1.566 rs6000.c
--- gcc/config/rs6000/rs6000.c      7 Jan 2004 01:21:27 -0000     1.566
+++ gcc/config/rs6000/rs6000.c      7 Jan 2004 10:28:29 -0000
@@ -1676,8 +1676,27 @@ easy_vector_constant (rtx op, enum machi
       && cst2 >= -0x7fff && cst2 <= 0x7fff)
     return 1;

-  if (TARGET_ALTIVEC && EASY_VECTOR_15 (cst, op, mode))
-    return 1;
+  if (TARGET_ALTIVEC)
+    switch (mode)
+      {
+      case V4SImode:
+     if (EASY_VECTOR_15 (cst, op, mode))
+       return 1;
+     if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
+       break;
+     cst = cst >> 16;
+      case V8HImode:
+     if (EASY_VECTOR_15 (cst, op, mode))
+       return 1;
+     if ((cst & 0xff) != ((cst >> 8) & 0xff))
+       break;
+     cst = cst >> 8;
+      case V16QImode:
+     if (EASY_VECTOR_15 (cst, op, mode))
+       return 1;
+      default:
+     break;
+      }

   if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode))
     return 1;
@@ -1718,23 +1737,37 @@ output_vec_const_move (rtx *operands)
     {
       if (zero_constant (vec, mode))
      return "vxor %0,%0,%0";
-      else if (EASY_VECTOR_15 (cst, vec, mode))
+      else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
+     return "#";
+      else if (easy_vector_constant (vec, mode))
      {
        operands[1] = GEN_INT (cst);
        switch (mode)
          {
          case V4SImode:
-           return "vspltisw %0,%1";
+           if (EASY_VECTOR_15 (cst, vec, mode))
+           {
+             operands[1] = GEN_INT (cst);
+             return "vspltisw %0,%1";
+           }
+           cst = cst >> 16;
          case V8HImode:
-           return "vspltish %0,%1";
+           if (EASY_VECTOR_15 (cst, vec, mode))
+           {
+             operands[1] = GEN_INT (cst);
+             return "vspltish %0,%1";
+           }
+           cst = cst >> 8;
          case V16QImode:
-           return "vspltisb %0,%1";
+           if (EASY_VECTOR_15 (cst, vec, mode))
+           {
+             operands[1] = GEN_INT (cst);
+             return "vspltisb %0,%1";
+           }
          default:
            abort ();
          }
      }
-      else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
-     return "#";
       else
      abort ();
     }

altivec-11.c:

/* { dg-do compile { target powerpc*-*-* } } */
/* { dg-options "-O2 -maltivec -mabi=altivec" } */
/* { dg-final { scan-assembler-not "lvx" } } */
#include <altivec.h>

void foo (vector int);
void foo_s (vector short);
void foo_c (vector char);

/* All constants should be loaded into vector register without
   load from memory.  */
void
bar (void)
{
  foo ((vector int) {0, 0, 0, 0});
  foo ((vector int) {1, 1, 1, 1});
  foo ((vector int) {15, 15, 15, 15});
  foo ((vector int) {-16, -16, -16, -16});
  foo ((vector int) {0x10001, 0x10001, 0x10001, 0x10001});
  foo ((vector int) {0xf000f, 0xf000f, 0xf000f, 0xf000f});
  foo ((vector int) {0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0});
  foo ((vector int) {0x1010101, 0x1010101, 0x1010101, 0x1010101});
  foo ((vector int) {0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f});
  foo ((vector int) {0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0});
  foo ((vector int) {0x10, 0x10, 0x10, 0x10});
  foo ((vector int) {0x1e, 0x1e, 0x1e, 0x1e});

  foo_s ((vector short int) {0, 0, 0, 0, 0, 0, 0, 0});
  foo_s ((vector short int) {1, 1, 1, 1, 1, 1, 1, 1});
  foo_s ((vector short int) {15, 15, 15, 15, 15, 15, 15, 15});
  foo_s ((vector short int) {-16, -16, -16, -16, -16, -16, -16, -16});
  foo_s ((vector short int) {0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0,
                         0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0});
  foo_s ((vector short int) {0xf0f, 0xf0f, 0xf0f, 0xf0f,
                         0xf0f, 0xf0f, 0xf0f, 0xf0f});

  foo_c ((vector char) {0, 0, 0, 0, 0, 0, 0, 0,
                    0, 0, 0, 0, 0, 0, 0, 0});
  foo_c ((vector char) {1, 1, 1, 1, 1, 1, 1, 1,
                    1, 1, 1, 1, 1, 1, 1, 1});
  foo_c ((vector char) {15, 15, 15, 15, 15, 15, 15, 15,
                    15, 15, 15, 15, 15, 15, 15, 15});
  foo_c ((vector char) {-16, -16, -16, -16, -16, -16, -16, -16,
                    -16, -16, -16, -16, -16, -16, -16, -16});
}



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