This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [csl-arm-branch] Add sign/zero extend instructions.

> The attached patch adds patterns for the armv6 sign/zero extend instructions, 
> including the extend and add insns.
> It currently only implements the unrotated variants.
> Tested with cross-compiler to arm-none-elf/mcpu=arm1136js.
> Ok?
> Paul
> 2003-12-23  Paul Brook  <>
> 	* config/arm/arm.c (arm_arch6j): New variable.
> 	(arm_override_options): Set it.
> 	(arm_emit_extendsi): New function.
> 	* config/arm/arm-protos.h (arm_emit_extendsi): Add prototype.
> 	* config/arm/arm.h (arm_arch6j): Declare.
> 	* config/arm/ Add sign/zero extend insns.


I don't think the arm_emit_extendsi function is safe -- you shouldn't be 
modifying part of an operand passed into an expander, since you don't know 
what else might be using it.  Secondly, I don't think you should be 
restricting this to

  (subreg:HI (reg:SI) 0)

It should be perfectly ok to match


as well (this gives the optimizer more freedom).

Further, the load-extend and simple register-extend operations should 
share a common pattern -- then if reloading is needed the compiler can 
simply do the right thing -- without that we might end up with sequences 

	ldrh	r0, [stack slot]
	uxth	r0, r0

The second instruction is redundant.

Finally, you'd missed the attributes off the new patterns, so the compiler 
didn't know the size or the scheduling requirements.

Just for the moment I've classified these instructions as alu_shift (the 
arm11 manual suggests they have an early reg as a shift operand would do, 
but I need to enquire further whether that is really the case).

I've fixed all the above problems and checked in the new code.


2004-01-07  Richard Earnshaw  <>

	* arm.c (arm_emit_extendsi): Delete.
	* arm-protos.h (arm_emit_extendsi): Delete.
	* (zero_extendhisi2): Also handle zero-extension of 
	(zero_extendqisi2, extendhisi2, extendqisi2): Likewise.
	(thumb_zero_extendhisi2): Only match if not v6.
	(arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2)
	(thumb_extendhisi2, arm_extendhisi2, arm_extendqisi)
	(thumb_extendqisi2): Likewise.
	(thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns.
	(thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns.
	(thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns.
	(thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns.
	(arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete.
	(arm_extendhisi2_reg, arm_extendqisi2_reg): Delete.
	(arm_zero_extendhisi2addsi): Remove subreg.  Add attributes.
	(arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise.
	(arm_extendqisi2addsi): Likewise.

Attachment: v6xt.patch
Description: v6xt.patch

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]