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Fix si->tf & tf->si conversions for 32-bit mode


When -mlong-double-128 was used with simple test programs like

long foo (long double a)
{
  return a;
}

and

long double foo (long a)
{
  return a;
}

the compiler ICEd, because the splitters weren't allocating any
clobbers for the df->si and si->df conversions.

This fixes the ICE.

However, the tf->si code is still broken, because it computes the wrong
results.  That will be the subject of a later patch, which will
include a testcase.  (This was found while building libgcc with
-mlong-double-128, which I'll also send a patch for.)
The df->tf code is also broken, there's a reason that the move
expanders don't use fsub to load 0.0 into a FP register, that will
also be a later patch.

Bootstrapped & tested on powerpc-darwin, running dejagnu both with and
without -mlong-double-128, with one additional patch to provide
the needed library routines for 128-bit long double, and another patch
to support SUBREGs.

-- 
- Geoffrey Keating <geoffk@apple.com>

===File ~/patches/rs6000-longdoubleitod.patch===============
2004-01-06  Geoffrey Keating  <geoffk@apple.com>

	* config/rs6000/rs6000.md (floatsitf2): Use expand_float rather
	than trying to generate RTL directly.
	(fix_trunctfsi2): Use expand_fix rather than trying to generate
	RTL directly.

Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.279
diff -u -p -c -p -r1.279 rs6000.md
*** config/rs6000/rs6000.md	31 Dec 2003 00:25:51 -0000	1.279
--- config/rs6000/rs6000.md	6 Jan 2004 20:21:18 -0000
***************
*** 8290,8308 ****
  	(float_extend:TF (match_dup 2)))]
    "")
  
! (define_insn_and_split "floatsitf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
!         (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
!    (clobber (match_scratch:DF 2 "=f"))]
    "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
     && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
!   "#"
!   "&& reload_completed"
!   [(set (match_dup 2)
! 	(float:DF (match_dup 1)))
!    (set (match_dup 0)
! 	(float_extend:TF (match_dup 2)))]
!   "")
  
  (define_insn_and_split "fix_trunctfdi2"
    [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
--- 8290,8306 ----
  	(float_extend:TF (match_dup 2)))]
    "")
  
! (define_expand "floatsitf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
!         (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
    "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
     && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
! {
!   rtx tmp = gen_reg_rtx (DFmode);
!   expand_float (tmp, operands[1], false);
!   emit_insn (gen_extenddftf2 (operands[0], tmp));
!   DONE;
! })
  
  (define_insn_and_split "fix_trunctfdi2"
    [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
***************
*** 8319,8337 ****
  	(fix:DI (match_dup 2)))]
    "")
  
! (define_insn_and_split "fix_trunctfsi2"
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
!         (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
!    (clobber (match_scratch:DF 2 "=f"))]
    "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
     && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
!   "#"
!   "&& reload_completed"
!   [(set (match_dup 2)
! 	(float_truncate:DF (match_dup 1)))
!    (set (match_dup 0)
! 	(fix:SI (match_dup 2)))]
!   "")
  
  (define_insn "negtf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
--- 8317,8333 ----
  	(fix:DI (match_dup 2)))]
    "")
  
! (define_expand "fix_trunctfsi2"
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
!         (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
    "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
     && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
! {
!   rtx tmp = gen_reg_rtx (DFmode);
!   emit_insn (gen_trunctfdf2 (tmp, operands[1]));
!   expand_fix (operands[0], tmp, false);
!   DONE;
! })
  
  (define_insn "negtf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
============================================================


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