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[patch] m32r.md: Fix PR target/13380.


Hi,

Attached is a patch to fix PR target/13380.

Consider the following test case.

void
foo (unsigned int a, unsigned int b)
{
  if (a > b)
    {
      while (a)
	{
	  switch (b)
	    {
	    default:
	      a = 0;
	    case 2:
	      a = 0;
	    case 1:
	      a = 0;
	    case 0:
	      ;
	    }
	}
    }
}

While the loop optimizer tries to move an invariant out of the loop,
it will generate the following unrecognized insn, which later causes
an ICE.

(set (reg:SI 29)
     (ltu:SI (reg/v:SI 26)
	     (const_int 1)))

This originally looks like so

(set (reg:SI 17 cbit)
     (ltu:SI (reg/v:SI 26)
	     (const_int 1)))

Note that (reg:SI 17) is a condition code register.  Not knowing
(reg:SI 17) is a special register, the loop optimizer replaces the
destination with a pseudo reg.

The patch fixes this problem by replacing (reg:SI 17) with (reg:CC 17)
throughout m32r.md.  This way, the loop optimizer (and others) will
never mix up the condition code register with an ordinary register.
There are a few places where I do a little more than simple
replacement.  Specifically,

(set (match_operand:SI ...)
     (reg:SI 17))

is replaced with

(set (match_operand:SI ...)
     (ne:SI (reg:CC 17) (const_int 0)))

so that modes will match.

Tested on m32r-elf on top of

http://gcc.gnu.org/ml/gcc-patches/2003-12/msg01900.html

OK to apply?

Kazu Hirata

2004-01-01  Kazu Hirata  <kazu@cs.umass.edu>

	PR target/13380.
	* config/m32r/m32r.md: Replace (reg:SI 17) with (reg:CC 17)
	or (ne:SI (reg:CC 17) (const_int 0)).
	Be specific about modes wherever possible.

2004-01-01  Kazu Hirata  <kazu@cs.umass.edu>

	PR target/13380.
	* gcc.c-torture/compile/20040101-1.c: New.

Index: m32r.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m32r/m32r.md,v
retrieving revision 1.35
diff -u -r1.35 m32r.md
*** m32r.md	31 Dec 2003 10:33:02 -0000	1.35
--- m32r.md	1 Jan 2004 02:03:32 -0000
***************
*** 579,585 ****
  
  (define_insn "*load_sda_base"
    [(set (match_operand:SI 0 "register_operand" "=r")
! 	(unspec [(const_int 0)] 2))]
    ""
    "ld24 %0,#_SDA_BASE_"
    [(set_attr "type" "int4")
--- 579,585 ----
  
  (define_insn "*load_sda_base"
    [(set (match_operand:SI 0 "register_operand" "=r")
! 	(unspec:SI [(const_int 0)] 2))]
    ""
    "ld24 %0,#_SDA_BASE_"
    [(set_attr "type" "int4")
***************
*** 900,906 ****
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(plus:DI (match_operand:DI 1 "register_operand" "%0")
  		 (match_operand:DI 2 "register_operand" "r")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 900,906 ----
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(plus:DI (match_operand:DI 1 "register_operand" "%0")
  		 (match_operand:DI 2 "register_operand" "r")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 911,933 ****
    [(set (match_operand:DI 0 "register_operand" "")
  	(plus:DI (match_operand:DI 1 "register_operand" "")
  		 (match_operand:DI 2 "register_operand" "")))
!    (clobber (match_operand 3 "" ""))]
    "reload_completed"
!   [(parallel [(set (match_dup 3)
  		   (const_int 0))
  	      (use (match_dup 4))])
     (parallel [(set (match_dup 4)
  		   (plus:SI (match_dup 4)
  			    (plus:SI (match_dup 5)
! 				     (match_dup 3))))
! 	      (set (match_dup 3)
! 		   (unspec [(const_int 0)] 3))])
     (parallel [(set (match_dup 6)
  		   (plus:SI (match_dup 6)
  			    (plus:SI (match_dup 7)
! 				     (match_dup 3))))
! 	      (set (match_dup 3)
! 		   (unspec [(const_int 0)] 3))])]
    "
  {
    operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
--- 911,933 ----
    [(set (match_operand:DI 0 "register_operand" "")
  	(plus:DI (match_operand:DI 1 "register_operand" "")
  		 (match_operand:DI 2 "register_operand" "")))
!    (clobber (reg:CC 17))]
    "reload_completed"
!   [(parallel [(set (reg:CC 17)
  		   (const_int 0))
  	      (use (match_dup 4))])
     (parallel [(set (match_dup 4)
  		   (plus:SI (match_dup 4)
  			    (plus:SI (match_dup 5)
! 				     (ne:SI (reg:CC 17) (const_int 0)))))
! 	      (set (reg:CC 17)
! 		   (unspec:CC [(const_int 0)] 3))])
     (parallel [(set (match_dup 6)
  		   (plus:SI (match_dup 6)
  			    (plus:SI (match_dup 7)
! 				     (ne:SI (reg:CC 17) (const_int 0)))))
! 	      (set (reg:CC 17)
! 		   (unspec:CC [(const_int 0)] 3))])]
    "
  {
    operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
***************
*** 937,943 ****
  }")
  
  (define_insn "*clear_c"
!   [(set (reg:SI 17)
  	(const_int 0))
     (use (match_operand:SI 0 "register_operand" "r"))]
    ""
--- 937,943 ----
  }")
  
  (define_insn "*clear_c"
!   [(set (reg:CC 17)
  	(const_int 0))
     (use (match_operand:SI 0 "register_operand" "r"))]
    ""
***************
*** 949,957 ****
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(plus:SI (match_operand:SI 1 "register_operand" "%0")
  		 (plus:SI (match_operand:SI 2 "register_operand" "r")
! 			  (reg:SI 17))))
!    (set (reg:SI 17)
! 	(unspec [(const_int 0)] 3))]
    ""
    "addx %0,%2"
    [(set_attr "type" "int2")
--- 949,957 ----
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(plus:SI (match_operand:SI 1 "register_operand" "%0")
  		 (plus:SI (match_operand:SI 2 "register_operand" "r")
! 			  (ne:SI (reg:CC 17) (const_int 0)))))
!    (set (reg:CC 17)
! 	(unspec:CC [(const_int 0)] 3))]
    ""
    "addx %0,%2"
    [(set_attr "type" "int2")
***************
*** 970,976 ****
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(minus:DI (match_operand:DI 1 "register_operand" "0")
  		  (match_operand:DI 2 "register_operand" "r")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 970,976 ----
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(minus:DI (match_operand:DI 1 "register_operand" "0")
  		  (match_operand:DI 2 "register_operand" "r")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 981,1003 ****
    [(set (match_operand:DI 0 "register_operand" "")
  	(minus:DI (match_operand:DI 1 "register_operand" "")
  		  (match_operand:DI 2 "register_operand" "")))
!    (clobber (match_operand 3 "" ""))]
    "reload_completed"
!   [(parallel [(set (match_dup 3)
  		   (const_int 0))
  	      (use (match_dup 4))])
     (parallel [(set (match_dup 4)
  		   (minus:SI (match_dup 4)
  			     (minus:SI (match_dup 5)
! 				       (match_dup 3))))
! 	      (set (match_dup 3)
! 		   (unspec [(const_int 0)] 3))])
     (parallel [(set (match_dup 6)
  		   (minus:SI (match_dup 6)
  			     (minus:SI (match_dup 7)
! 				       (match_dup 3))))
! 	      (set (match_dup 3)
! 		   (unspec [(const_int 0)] 3))])]
    "
  {
    operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
--- 981,1003 ----
    [(set (match_operand:DI 0 "register_operand" "")
  	(minus:DI (match_operand:DI 1 "register_operand" "")
  		  (match_operand:DI 2 "register_operand" "")))
!    (clobber (reg:CC 17))]
    "reload_completed"
!   [(parallel [(set (reg:CC 17)
  		   (const_int 0))
  	      (use (match_dup 4))])
     (parallel [(set (match_dup 4)
  		   (minus:SI (match_dup 4)
  			     (minus:SI (match_dup 5)
! 				       (ne:SI (reg:CC 17) (const_int 0)))))
! 	      (set (reg:CC 17)
! 		   (unspec:CC [(const_int 0)] 3))])
     (parallel [(set (match_dup 6)
  		   (minus:SI (match_dup 6)
  			     (minus:SI (match_dup 7)
! 				       (ne:SI (reg:CC 17) (const_int 0)))))
! 	      (set (reg:CC 17)
! 		   (unspec:CC [(const_int 0)] 3))])]
    "
  {
    operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
***************
*** 1010,1018 ****
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(minus:SI (match_operand:SI 1 "register_operand" "%0")
  		  (minus:SI (match_operand:SI 2 "register_operand" "r")
! 			    (reg:SI 17))))
!    (set (reg:SI 17)
! 	(unspec [(const_int 0)] 3))]
    ""
    "subx %0,%2"
    [(set_attr "type" "int2")
--- 1010,1018 ----
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(minus:SI (match_operand:SI 1 "register_operand" "%0")
  		  (minus:SI (match_operand:SI 2 "register_operand" "r")
! 			    (ne:SI (reg:CC 17) (const_int 0)))))
!    (set (reg:CC 17)
! 	(unspec:CC [(const_int 0)] 3))]
    ""
    "subx %0,%2"
    [(set_attr "type" "int2")
***************
*** 1241,1247 ****
  ;; preferred.
  
  (define_expand "cmpsi"
!   [(set (reg:SI 17)
  	(compare:CC (match_operand:SI 0 "register_operand" "")
  		    (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
    ""
--- 1241,1247 ----
  ;; preferred.
  
  (define_expand "cmpsi"
!   [(set (reg:CC 17)
  	(compare:CC (match_operand:SI 0 "register_operand" "")
  		    (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
    ""
***************
*** 1253,1260 ****
  }")
  
  (define_insn "cmp_eqsi_zero_insn"
!   [(set (reg:SI 17)
!         (eq:SI (match_operand:SI 0 "register_operand" "r,r")
                 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
    "TARGET_M32RX || TARGET_M32R2"
    "@
--- 1253,1260 ----
  }")
  
  (define_insn "cmp_eqsi_zero_insn"
!   [(set (reg:CC 17)
!         (eq:CC (match_operand:SI 0 "register_operand" "r,r")
                 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
    "TARGET_M32RX || TARGET_M32R2"
    "@
***************
*** 1268,1275 ****
  ;; is quite inefficient.  However, it is rarely used.
  
  (define_insn "cmp_eqsi_insn"
!   [(set (reg:SI 17)
!         (eq:SI (match_operand:SI 0 "register_operand" "r,r")
                 (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
     (clobber (match_scratch:SI 2 "=&r,&r"))]
    ""
--- 1268,1275 ----
  ;; is quite inefficient.  However, it is rarely used.
  
  (define_insn "cmp_eqsi_insn"
!   [(set (reg:CC 17)
!         (eq:CC (match_operand:SI 0 "register_operand" "r,r")
                 (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
     (clobber (match_scratch:SI 2 "=&r,&r"))]
    ""
***************
*** 1293,1300 ****
     (set_attr "length" "8,8")])
  
  (define_insn "cmp_ltsi_insn"
!   [(set (reg:SI 17)
!         (lt:SI (match_operand:SI 0 "register_operand" "r,r")
                 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
    ""
    "@
--- 1293,1300 ----
     (set_attr "length" "8,8")])
  
  (define_insn "cmp_ltsi_insn"
!   [(set (reg:CC 17)
!         (lt:CC (match_operand:SI 0 "register_operand" "r,r")
                 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
    ""
    "@
***************
*** 1304,1311 ****
     (set_attr "length" "2,4")])
  
  (define_insn "cmp_ltusi_insn"
!   [(set (reg:SI 17)
!         (ltu:SI (match_operand:SI 0 "register_operand" "r,r")
                  (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
    ""
    "@
--- 1304,1311 ----
     (set_attr "length" "2,4")])
  
  (define_insn "cmp_ltusi_insn"
!   [(set (reg:CC 17)
!         (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
                  (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
    ""
    "@
***************
*** 1696,1702 ****
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(eq:SI (match_operand:SI 1 "register_operand" "%r")
  	       (match_operand:SI 2 "reg_or_zero_operand" "rP")))
!    (clobber (reg:SI 17))]
    "TARGET_M32RX || TARGET_M32R2"
    "#"
    [(set_attr "type" "multi")
--- 1696,1702 ----
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(eq:SI (match_operand:SI 1 "register_operand" "%r")
  	       (match_operand:SI 2 "reg_or_zero_operand" "rP")))
!    (clobber (reg:CC 17))]
    "TARGET_M32RX || TARGET_M32R2"
    "#"
    [(set_attr "type" "multi")
***************
*** 1706,1725 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(eq:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_zero_operand" "")))
!    (clobber (reg:SI 17))]
    "TARGET_M32RX || TARGET_M32R2"
!   [(set (reg:SI 17)
! 	(eq:SI (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(reg:SI 17))]
    "")
  
  (define_insn "seq_zero_insn"
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(eq:SI (match_operand:SI 1 "register_operand" "r")
  	       (const_int 0)))
!    (clobber (reg:SI 17))]
    "TARGET_M32R"
    "#"
    [(set_attr "type" "multi")
--- 1706,1725 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(eq:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_zero_operand" "")))
!    (clobber (reg:CC 17))]
    "TARGET_M32RX || TARGET_M32R2"
!   [(set (reg:CC 17)
! 	(eq:CC (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))]
    "")
  
  (define_insn "seq_zero_insn"
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(eq:SI (match_operand:SI 1 "register_operand" "r")
  	       (const_int 0)))
!    (clobber (reg:CC 17))]
    "TARGET_M32R"
    "#"
    [(set_attr "type" "multi")
***************
*** 1729,1735 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(eq:SI (match_operand:SI 1 "register_operand" "")
  	       (const_int 0)))
!    (clobber (reg:SI 17))]
    "TARGET_M32R"
    [(match_dup 3)]
    "
--- 1729,1735 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(eq:SI (match_operand:SI 1 "register_operand" "")
  	       (const_int 0)))
!    (clobber (reg:CC 17))]
    "TARGET_M32R"
    [(match_dup 3)]
    "
***************
*** 1748,1754 ****
    [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
  	(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
  	       (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
!    (clobber (reg:SI 17))
     (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
    "TARGET_M32R"
    "#"
--- 1748,1754 ----
    [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
  	(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
  	       (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
!    (clobber (reg:CC 17))
     (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
    "TARGET_M32R"
    "#"
***************
*** 1759,1765 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(eq:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
!    (clobber (reg:SI 17))
     (clobber (match_scratch:SI 3 ""))]
    "TARGET_M32R && reload_completed"
    [(match_dup 4)]
--- 1759,1765 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(eq:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
!    (clobber (reg:CC 17))
     (clobber (match_scratch:SI 3 ""))]
    "TARGET_M32R && reload_completed"
    [(match_dup 4)]
***************
*** 1837,1843 ****
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(ne:SI (match_operand:SI 1 "register_operand" "r")
  	       (const_int 0)))
!    (clobber (reg:SI 17))
     (clobber (match_scratch:SI 2 "=&r"))]
    ""
    "#"
--- 1837,1843 ----
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(ne:SI (match_operand:SI 1 "register_operand" "r")
  	       (const_int 0)))
!    (clobber (reg:CC 17))
     (clobber (match_scratch:SI 2 "=&r"))]
    ""
    "#"
***************
*** 1848,1863 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(ne:SI (match_operand:SI 1 "register_operand" "")
  	       (const_int 0)))
!    (clobber (reg:SI 17))
     (clobber (match_scratch:SI 2 ""))]
    "reload_completed"
    [(set (match_dup 2)
  	(const_int 0))
!    (set (reg:SI 17)
! 	(ltu:SI (match_dup 2)
  		(match_dup 1)))
     (set (match_dup 0)
! 	(reg:SI 17))]
    "")
  	
  (define_expand "slt"
--- 1848,1863 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(ne:SI (match_operand:SI 1 "register_operand" "")
  	       (const_int 0)))
!    (clobber (reg:CC 17))
     (clobber (match_scratch:SI 2 ""))]
    "reload_completed"
    [(set (match_dup 2)
  	(const_int 0))
!    (set (reg:CC 17)
! 	(ltu:CC (match_dup 2)
  		(match_dup 1)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))]
    "")
  	
  (define_expand "slt"
***************
*** 1887,1893 ****
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(lt:SI (match_operand:SI 1 "register_operand" "r,r")
  	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 1887,1893 ----
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(lt:SI (match_operand:SI 1 "register_operand" "r,r")
  	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 1897,1909 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(lt:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:SI 17))]
    ""
!   [(set (reg:SI 17)
! 	(lt:SI (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(reg:SI 17))]
    "")
  
  (define_expand "sle"
--- 1897,1909 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(lt:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:CC 17))]
    ""
!   [(set (reg:CC 17)
! 	(lt:CC (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))]
    "")
  
  (define_expand "sle"
***************
*** 1950,1956 ****
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(le:SI (match_operand:SI 1 "register_operand" "r")
  	       (match_operand:SI 2 "register_operand" "r")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 1950,1956 ----
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(le:SI (match_operand:SI 1 "register_operand" "r")
  	       (match_operand:SI 2 "register_operand" "r")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 1960,1972 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(le:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:SI 17))]
    "!optimize_size"
!   [(set (reg:SI 17)
! 	(lt:SI (match_dup 2)
  	       (match_dup 1)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
--- 1960,1972 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(le:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:CC 17))]
    "!optimize_size"
!   [(set (reg:CC 17)
! 	(lt:CC (match_dup 2)
  	       (match_dup 1)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
***************
*** 1978,1990 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(le:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:SI 17))]
    "optimize_size"
!   [(set (reg:SI 17)
! 	(lt:SI (match_dup 2)
  	       (match_dup 1)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
--- 1978,1990 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(le:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:CC 17))]
    "optimize_size"
!   [(set (reg:CC 17)
! 	(lt:CC (match_dup 2)
  	       (match_dup 1)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
***************
*** 2042,2048 ****
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(ge:SI (match_operand:SI 1 "register_operand" "r,r")
  	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 2042,2048 ----
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(ge:SI (match_operand:SI 1 "register_operand" "r,r")
  	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 2052,2064 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(ge:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:SI 17))]
    "!optimize_size"
!   [(set (reg:SI 17)
! 	(lt:SI (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
--- 2052,2064 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(ge:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:CC 17))]
    "!optimize_size"
!   [(set (reg:CC 17)
! 	(lt:CC (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
***************
*** 2070,2082 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(ge:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:SI 17))]
    "optimize_size"
!   [(set (reg:SI 17)
! 	(lt:SI (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
--- 2070,2082 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(ge:SI (match_operand:SI 1 "register_operand" "")
  	       (match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:CC 17))]
    "optimize_size"
!   [(set (reg:CC 17)
! 	(lt:CC (match_dup 1)
  	       (match_dup 2)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
***************
*** 2111,2117 ****
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
  		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 2111,2117 ----
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
  		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 2121,2133 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(ltu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:SI 17))]
    ""
!   [(set (reg:SI 17)
! 	(ltu:SI (match_dup 1)
  		(match_dup 2)))
     (set (match_dup 0)
! 	(reg:SI 17))]
    "")
  
  (define_expand "sleu"
--- 2121,2133 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(ltu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:CC 17))]
    ""
!   [(set (reg:CC 17)
! 	(ltu:CC (match_dup 1)
  		(match_dup 2)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))]
    "")
  
  (define_expand "sleu"
***************
*** 2171,2177 ****
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(leu:SI (match_operand:SI 1 "register_operand" "r")
  		(match_operand:SI 2 "register_operand" "r")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 2171,2177 ----
    [(set (match_operand:SI 0 "register_operand" "=r")
  	(leu:SI (match_operand:SI 1 "register_operand" "r")
  		(match_operand:SI 2 "register_operand" "r")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 2181,2193 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(leu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:SI 17))]
    "!optimize_size"
!   [(set (reg:SI 17)
! 	(ltu:SI (match_dup 2)
  		(match_dup 1)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
--- 2181,2193 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(leu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:CC 17))]
    "!optimize_size"
!   [(set (reg:CC 17)
! 	(ltu:CC (match_dup 2)
  		(match_dup 1)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
***************
*** 2199,2211 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(leu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:SI 17))]
    "optimize_size"
!   [(set (reg:SI 17)
! 	(ltu:SI (match_dup 2)
  		(match_dup 1)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
--- 2199,2211 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(leu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "register_operand" "")))
!    (clobber (reg:CC 17))]
    "optimize_size"
!   [(set (reg:CC 17)
! 	(ltu:CC (match_dup 2)
  		(match_dup 1)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
***************
*** 2263,2269 ****
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(geu:SI (match_operand:SI 1 "register_operand" "r,r")
  		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:SI 17))]
    ""
    "#"
    [(set_attr "type" "multi")
--- 2263,2269 ----
    [(set (match_operand:SI 0 "register_operand" "=r,r")
  	(geu:SI (match_operand:SI 1 "register_operand" "r,r")
  		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
!    (clobber (reg:CC 17))]
    ""
    "#"
    [(set_attr "type" "multi")
***************
*** 2273,2285 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(geu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:SI 17))]
    "!optimize_size"
!   [(set (reg:SI 17)
! 	(ltu:SI (match_dup 1)
  		(match_dup 2)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
--- 2273,2285 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(geu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:CC 17))]
    "!optimize_size"
!   [(set (reg:CC 17)
! 	(ltu:CC (match_dup 1)
  		(match_dup 2)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(xor:SI (match_dup 0)
  		(const_int 1)))]
***************
*** 2291,2303 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(geu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:SI 17))]
    "optimize_size"
!   [(set (reg:SI 17)
! 	(ltu:SI (match_dup 1)
  		(match_dup 2)))
     (set (match_dup 0)
! 	(reg:SI 17))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
--- 2291,2303 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(geu:SI (match_operand:SI 1 "register_operand" "")
  		(match_operand:SI 2 "reg_or_int16_operand" "")))
!    (clobber (reg:CC 17))]
    "optimize_size"
!   [(set (reg:CC 17)
! 	(ltu:CC (match_dup 1)
  		(match_dup 2)))
     (set (match_dup 0)
! 	(ne:SI (reg:CC 17) (const_int 0)))
     (set (match_dup 0)
  	(plus:SI (match_dup 0)
  		 (const_int -1)))
***************
*** 2307,2313 ****
  
  (define_insn "movcc_insn"
    [(set (match_operand:SI 0 "register_operand" "=r")
! 	(reg:SI 17))]
    ""
    "mvfc %0, cbr"
    [(set_attr "type" "misc")
--- 2307,2313 ----
  
  (define_insn "movcc_insn"
    [(set (match_operand:SI 0 "register_operand" "=r")
! 	(ne:SI (reg:CC 17) (const_int 0)))]
    ""
    "mvfc %0, cbr"
    [(set_attr "type" "misc")
--- /dev/null	2003-09-15 09:40:47.000000000 -0400
+++ 20040101-1.c	2003-12-31 21:45:37.000000000 -0500
@@ -0,0 +1,25 @@
+/* PR target/13380.
+   On m32r, the condition code register, (reg:SI 17), is replaced with
+   a pseudo reg, which would cause an unrecognized insn.  */
+
+void
+foo (unsigned int a, unsigned int b)
+{
+  if (a > b)
+    {
+      while (a)
+	{
+	  switch (b)
+	    {
+	    default:
+	      a = 0;
+	    case 2:
+	      a = 0;
+	    case 1:
+	      a = 0;
+	    case 0:
+	      ;
+	    }
+	}
+    }
+}


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