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Re: [csl-arm-branch]: Better bypasses for 1026 and 1136 processors
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Nathan Sidwell <nathan at codesourcery dot com>
- Cc: Richard Earnshaw <rearnsha at arm dot com>, gcc-patches at gcc dot gnu dot org, Paul Brook <paul at codesourcery dot com>
- Date: Wed, 17 Dec 2003 11:47:29 +0000
- Subject: Re: [csl-arm-branch]: Better bypasses for 1026 and 1136 processors
- Organization: ARM Ltd.
- Reply-to: Richard dot Earnshaw at arm dot com
nathan@codesourcery.com said:
> 2003-12-16 Nathan Sidwell <nathan@codesourcery.com>
> * config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep):
> Declare.
> * config/arm/arm.c (arm_adjust_cost): Check shift cost for
> TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG.
> (arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep,
> arm_no_early_mul_dep): Correctly deal with conditional execution,
> parallels and single shift operations.
> (arm_no_early_alu_shift_value_dep): Define.
> * arm.md (attr type): Replace 'normal' with 'alu',
> 'alu_shift' and 'alu_shift_reg'.
> (attr core_cycles): Adjust.
> (*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3,
> *shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0,
> *not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp,
> *cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0,
> *arith_shiftsi_compare0_scratch, *sub_shiftsi,
> *sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch,
> *if_shift_move, *if_move_shift, *if_shift_shift): Set type
> attribute appropriately.
> * config/arm/arm1026ejs.md (alu_op): Adjust.
> (alu_shift_op, alu_shift_reg_op): New.
> * config/arm/arm1136.md: Add better bypasses for early
> registers. Remove load[234] and store[234] bypasses.
> (11_alu_op): Adjust.
> (11_alu_shift_op, 11_alu_shift_reg_op): New.
OK, except:
+ if (GET_CODE (value) == COND_EXEC)
+ value = XEXP (value, 1);
You should use COND_EXEC_CODE instead of XEXP here and all similar cases.
R.