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Re: [PATCH] GCSE after reload


Mostafa Hagog wrote:
> 
> The gcse-after-reload is performed after register allocation and reload,
> and its purpose is to remove redundant loads due to spilling and other
> optimizations that occur after gcse was performed.
> 
> The gcse-after-reload, try to find inter-block redundancies but only in
> those redundancies that caused by the immediate predecessor blocks.
> Since this is performed after the register allocation and reload, the
> redundancies are removed only if the register usage allows so.
> 
> In general this optimization considers every load in the given basic block
> and looks for loads or stores from the same memory location in the its
> immediate predecessors. It handles also partial redundancies by adding new
> loads on the edges if according to the feedback information it worth.
> 
> Testing:
> --------
> Bootstrap on powerpc-apple-darwin6.4
> Regression : g++, g77, libstdc++, libjava passed (no new failures).
>              gcc several tests reported as unexpected fails but behaved
>              as expected and the same as the vanilla, so I consider
>              these as OK too.
> 

Actually I was going to implement the same idea.  I believe that the
biggest improvement we can get for gcc with small or moderate amount of
registers would be in improvement of register allocation.  Reload is a
part of this.

I was thinking to implement redundant expression elimination based on
expression availability with interface analogous to cselib (so it could
be used in other parts of compiler too).

As for your implementation, it could work for RISC architecture but not
for CISC because you remove only load insn.  CISC insn (like x86) could
make load implicitly when the insn addresses a memory.

Another thing, reload can make a simple rematerialization, so it is
better to implement general gcse to get more improvement.

In any case, the patch is a step to the right direction.

I am just wondering what kind of improvement you get for powerpc with
this patch (I'd expect a good improvement for x86 if it were implemented
as I wrote).  IMHO, you should post this information in any case because
the patch is a new optimization.

Vlad


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