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[MIPS PATCH RFA] make prefetch patterns respect offset
- From: cgd at broadcom dot com
- To: gcc-patches at gcc dot gnu dot org
- Date: 02 Oct 2003 16:15:39 -0700
- Subject: [MIPS PATCH RFA] make prefetch patterns respect offset
problem: when MIPS prefetch instructions were generated to be register
+ offset, the offset would be ignored. Not as useful as one might
like. 8-)
Tested in sources as of 2003-10-02 00:00 UTC (C only), no regressions.
Also seems to DTRT w/ some manual testing as well.
Is this a reasonable way to do this? (I *think* so, based on the fact
that other code also does operands[N] = const0_rtx; but i'm not sure.)
chris
--
2003-10-02 Chris Demetriou <cgd@broadcom.com>
* config/mips/mips.c (mips_emit_prefetch): Use operand 3
in instructions being output.
* config/mips/mips.md (prefetch_si_address): Change third
operand's constraint letter to 'I'.
(prefetch_di_address): Likewise.
(prefetch_si, prefetch_di): Set third operand to const0_rtx.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.318
diff -u -p -r1.318 mips.c
--- config/mips/mips.c 2 Oct 2003 00:44:24 -0000 1.318
+++ config/mips/mips.c 2 Oct 2003 23:11:18 -0000
@@ -9643,16 +9643,16 @@ mips_emit_prefetch (rtx *operands)
static const char * const alt[2][4] = {
{
- "pref\t4,%a0",
- "pref\t0,%a0",
- "pref\t0,%a0",
- "pref\t6,%a0"
+ "pref\t4,%3(%0)",
+ "pref\t0,%3(%0)",
+ "pref\t0,%3(%0)",
+ "pref\t6,%3(%0)"
},
{
- "pref\t5,%a0",
- "pref\t1,%a0",
- "pref\t1,%a0",
- "pref\t7,%a0"
+ "pref\t5,%3(%0)",
+ "pref\t1,%3(%0)",
+ "pref\t1,%3(%0)",
+ "pref\t7,%3(%0)"
}
};
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.196
diff -u -p -r1.196 mips.md
--- config/mips/mips.md 30 Sep 2003 07:14:39 -0000 1.196
+++ config/mips/mips.md 2 Oct 2003 23:11:18 -0000
@@ -8506,7 +8506,7 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j
(define_insn "prefetch_si_address"
[(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 3 "const_int_operand" "i"))
+ (match_operand:SI 3 "const_int_operand" "I"))
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == SImode"
@@ -8518,12 +8518,15 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == SImode"
- { return mips_emit_prefetch (operands); }
+{
+ operands[3] = const0_rtx;
+ return mips_emit_prefetch (operands);
+}
[(set_attr "type" "prefetch")])
(define_insn "prefetch_di_address"
[(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
- (match_operand:DI 3 "const_int_operand" "i"))
+ (match_operand:DI 3 "const_int_operand" "I"))
(match_operand:DI 1 "const_int_operand" "n")
(match_operand:DI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == DImode"
@@ -8535,7 +8538,10 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j
(match_operand:DI 1 "const_int_operand" "n")
(match_operand:DI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == DImode"
- { return mips_emit_prefetch (operands); }
+{
+ operands[3] = const0_rtx;
+ return mips_emit_prefetch (operands);
+}
[(set_attr "type" "prefetch")])
(define_insn "nop"