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Re: [patch] h8300: Fix target/11805


Kazu Hirata <kazu@cs.umass.edu> writes:
> Hi Zack,
>> I have been idly thinking about a model in which the initial RTL
>> claims that there is no condition code; instead there are
>> compare-and-branch insns that (if they were output) would produce a
>> pair of machine instructions.
...
> How would you represent a sequence where the result of subtraction is
> not needed?  Sometimes you don't want r0 to be destroyed like
>
>   cmpl r0, r1
>   beq  .L1
>
> That is,
>
>   if (r0 == r1) goto L1;

This would be just

  (set (pc)
       (if_then_else (eq:SI (reg:SI 0) (reg:SI 1))
                     (label_ref ".L1")
                     (pc)))

which leaves (reg:SI 0) unchanged.  The post-reload combine pass has
to be aware of where values die, but so does the existing one.

zw


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