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[patch] config: Follow spelling conventions.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 15 Jun 2003 03:51:48 -0400 (EDT)
- Subject: [patch] config: Follow spelling conventions.
Hi,
Attached is a patch to follow spelling conventions.
Committed as obvious.
Kazu Hirata
2003-06-15 Kazu Hirata <kazu@cs.umass.edu>
* config/alpha/alpha.md: Follow spelling conventions.
* config/arm/arm.c: Likewise.
* config/arm/arm.h: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/crtn.asm: Likewise.
* config/m32r/m32r.c: Likewise.
* config/m32r/m32r.md: Likewise.
* config/rs6000/rs6000.c: Likewise.
Index: alpha/alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.207
diff -u -r1.207 alpha.md
--- alpha/alpha.md 30 Mar 2003 19:00:12 -0000 1.207
+++ alpha/alpha.md 15 Jun 2003 07:44:37 -0000
@@ -5273,7 +5273,7 @@
;; Split the load of an address into a four-insn sequence on Unicos/Mk.
;; Always generate a REG_EQUAL note for the last instruction to facilitate
-;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
+;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
;; notes and update LABEL_NUSES because this is not done automatically.
;; Labels may be incorrectly deleted if we don't do this.
;;
Index: arm/arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.282
diff -u -r1.282 arm.c
--- arm/arm.c 15 Jun 2003 04:00:45 -0000 1.282
+++ arm/arm.c 15 Jun 2003 07:44:42 -0000
@@ -5642,7 +5642,7 @@
0))));
}
-/* Handle storing a half-word to memory during reload by synthesising as two
+/* Handle storing a half-word to memory during reload by synthesizing as two
byte stores. Take care not to clobber the input values until after we
have moved them somewhere safe. This code assumes that if the DImode
scratch in operands[2] overlaps either the input value or output address
@@ -7740,7 +7740,7 @@
it. If we are pushing other registers onto the stack however, we
can save an instruction in the epilogue by pushing the link register
now and then popping it back into the PC. This incurs extra memory
- accesses though, so we only do it when optimising for size, and only
+ accesses though, so we only do it when optimizing for size, and only
if we know that we will not need a fancy return sequence. */
if (regs_ever_live [LR_REGNUM]
|| (save_reg_mask
Index: arm/arm.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.196
diff -u -r1.196 arm.h
--- arm/arm.h 14 Jun 2003 21:47:40 -0000 1.196
+++ arm/arm.h 15 Jun 2003 07:44:44 -0000
@@ -2345,7 +2345,7 @@
#endif
/* Only perform branch elimination (by making instructions conditional) if
- we're optimising. Otherwise it's of no use anyway. */
+ we're optimizing. Otherwise it's of no use anyway. */
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
if (TARGET_ARM && optimize) \
arm_final_prescan_insn (INSN); \
Index: arm/arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.135
diff -u -r1.135 arm.md
--- arm/arm.md 2 Jun 2003 03:53:54 -0000 1.135
+++ arm/arm.md 15 Jun 2003 07:44:47 -0000
@@ -509,7 +509,7 @@
"
)
-; If there is a scratch available, this will be faster than synthesising the
+; If there is a scratch available, this will be faster than synthesizing the
; addition.
(define_peephole2
[(match_scratch:SI 3 "r")
Index: arm/crtn.asm
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/crtn.asm,v
retrieving revision 1.2
diff -u -r1.2 crtn.asm
--- arm/crtn.asm 28 Sep 2002 15:29:36 -0000 1.2
+++ arm/crtn.asm 15 Jun 2003 07:44:47 -0000
@@ -39,7 +39,7 @@
# in crti.asm. If you change this macro you must also change
# that macro match.
#
- # Note - we do not try any fancy optimisations of the return
+ # Note - we do not try any fancy optimizations of the return
# sequences here, it is just not worth it. Instead keep things
# simple. Restore all the save resgisters, including the link
# register and then perform the correct function return instruction.
Index: m32r/m32r.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m32r/m32r.c,v
retrieving revision 1.67
diff -u -r1.67 m32r.c
--- m32r/m32r.c 13 Jun 2003 16:57:26 -0000 1.67
+++ m32r/m32r.c 15 Jun 2003 07:44:48 -0000
@@ -1002,7 +1002,7 @@
return get_attr_length (op) != 2;
}
-/* Return non-zero if TYPE must be passed or returned in memory.
+/* Return nonzero if TYPE must be passed or returned in memory.
The m32r treats both directions the same so we handle both directions
in this function. */
Index: m32r/m32r.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m32r/m32r.md,v
retrieving revision 1.26
diff -u -r1.26 m32r.md
--- m32r/m32r.md 13 Jun 2003 04:18:26 -0000 1.26
+++ m32r/m32r.md 15 Jun 2003 07:44:49 -0000
@@ -2540,7 +2540,7 @@
;; Simialr code is produced for the subtract expression. With this
;; peephole the redundant move is eliminated.
;;
-;; This optimisation only works if PRESERVE_DEATH_INFO_REGNO_P is
+;; This optimization only works if PRESERVE_DEATH_INFO_REGNO_P is
;; defined in m32r.h
(define_peephole
Index: rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.491
diff -u -r1.491 rs6000.c
--- rs6000/rs6000.c 15 Jun 2003 07:36:41 -0000 1.491
+++ rs6000/rs6000.c 15 Jun 2003 07:44:55 -0000
@@ -1534,7 +1534,7 @@
abort ();
}
-/* Return non zero if all elements of a vector have the same value. */
+/* Return nonzero if all elements of a vector have the same value. */
static int
easy_vector_same (op, mode)