This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: target register load optimizations


Is there anything you're doing here that wouldn't be solved with a
register allocator that placed spill/fill code at optimal locations?
This is an NP-complete problem too, though easier to model using ILP.
See "Optimal spilling for CISC machines with few registers"		
I know we don't have that at the moment (even with new-ra), but in
theory would such an allocator completely obviate this pass?

Such an allocator would completely obviate the need for a lot of things :).

I don't see anywhere an explanation of why it would be useful to run
this code both before and after prologue generation.  Why wouldn't we
ONLY run the pass before prologue generation and be done with it?

You appear to be replicating a good part of df.c for this.  Is it
possible to re-use the existing insn scanning code instead?  How about
if df.c was enhanced to track only registers of a given class (with
ALL_REGS resulting in what it does now)?


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]