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[PATCH]: Fix of gcc HC11 options and reg class definition
- From: Stephane Carrez <stcarrez at nerim dot fr>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sat, 12 Apr 2003 17:22:37 +0200
- Subject: [PATCH]: Fix of gcc HC11 options and reg class definition
Hi!
I've committed this patch on 3_3 and mainline to fix:
- the -mnominmax switch was not working (it didn't cleared the flag)
- the -mnorelax switch is used by the HC11/HC12 specs but not recognized
- a reg class to represent the soft regs as well as Z reg is necessary for
some patterns which use 's' and 'z' constraint at the same time.
Stephane
2003-04-12 Stephane Carrez <stcarrez at nerim dot fr>
* config/m68hc11/m68hc11.h (TARGET_SWITCHES): Fix -mnominmax option;
recognize -mnorelax.
(reg_class): Add Z_OR_S_REGS to represent soft registers with Z
(REG_CLASS_NAMES): Add its name.
(REG_CLASS_CONTENTS): Define its content.
Index: config/m68hc11/m68hc11.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11.h,v
retrieving revision 1.55.4.9
diff -u -p -r1.55.4.9 m68hc11.h
--- config/m68hc11/m68hc11.h 24 Mar 2003 22:27:36 -0000 1.55.4.9
+++ config/m68hc11/m68hc11.h 12 Apr 2003 15:11:28 -0000
@@ -176,9 +176,9 @@ extern short *reg_renumber; /* def in lo
N_("Auto pre/post decrement increment allowed")}, \
{ "noauto-incdec", - MASK_AUTO_INC_DEC, \
N_("Auto pre/post decrement increment not allowed")}, \
- { "inmax", MASK_MIN_MAX, \
+ { "inmax", MASK_MIN_MAX, \
N_("Min/max instructions allowed")}, \
- { "nominmax", MASK_MIN_MAX, \
+ { "nominmax", - MASK_MIN_MAX, \
N_("Min/max instructions not allowed")}, \
{ "long-calls", MASK_LONG_CALLS, \
N_("Use call and rtc for function calls and returns")}, \
@@ -186,6 +186,8 @@ extern short *reg_renumber; /* def in lo
N_("Use jsr and rts for function calls and returns")}, \
{ "relax", MASK_NO_DIRECT_MODE, \
N_("Do not use direct addressing mode for soft registers")},\
+ { "norelax", -MASK_NO_DIRECT_MODE, \
+ N_("Use direct addressing mode for soft registers")}, \
{ "68hc11", MASK_M6811, \
N_("Compile for a 68HC11")}, \
{ "68hc12", MASK_M6812, \
@@ -571,6 +573,7 @@ enum reg_class
D_OR_S_REGS, /* 16-bit soft register or D register */
X_OR_S_REGS, /* 16-bit soft register or X register */
Y_OR_S_REGS, /* 16-bit soft register or Y register */
+ Z_OR_S_REGS, /* 16-bit soft register or Z register */
SP_OR_S_REGS, /* 16-bit soft register or SP register */
D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */
D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */
@@ -617,6 +620,7 @@ enum reg_class
"D_OR_S_REGS", \
"X_OR_S_REGS", \
"Y_OR_S_REGS", \
+ "Z_OR_S_REGS", \
"SP_OR_S_REGS", \
"D_OR_X_OR_S_REGS", \
"D_OR_Y_OR_S_REGS", \
@@ -685,6 +689,7 @@ enum reg_class
/* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \
/* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \
/* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \
+/* Z_OR_S_REGS */ { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */ \
/* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \
/* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \
/* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \