This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[patch] h8300.c: Tighten a predicate.


Hi,

Attached is a patch to tighten a predicate, bit_operand.

Currently, if rtx_equal_function_value_matters == 0, bit_operand
accepts more than what the insns using the predicate can handle.
Specifically, and:QI cannot take a memory operand with an offset, but
the current bit_operand says it can.  This results in bad code.  For
example

void
foo (unsigned long *p)
{
  if (*p & 0x80)
    bar ();
}

turns into

_foo:
	mov.b	@(3,er0),r2l
	and	#-128,r2l
	beq	.L1
	jsr	@_bar
.L1:
	rts

Rather than testing the sign bit by ANDing, we can simply use the sign
test like so

_foo:
	mov.b	@(3,er0),r2l
	bge	.L1
	jsr	@_bar
.L1:
	rts

Tested on h8300 port.  Committed.

Kazu Hirata

2003-03-01  Kazu Hirata  <kazu at cs dot umass dot edu>

	* config/h8300/h8300.c (bit_operand): Accept MEM only if it
	satisfies EXTRA_CONSTRAINT 'U'.

Index: h8300.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.c,v
retrieving revision 1.215
diff -u -r1.215 h8300.c
--- h8300.c	19 Feb 2003 21:21:21 -0000	1.215
+++ h8300.c	28 Feb 2003 14:26:26 -0000
@@ -980,12 +980,8 @@
     return 1;
   if (GET_CODE (op) == SUBREG)
     return 1;
-  if (!rtx_equal_function_value_matters)
-    /* We're building rtl.  */
-    return GET_CODE (op) == MEM;
-  else
-    return (GET_CODE (op) == MEM
-	    && EXTRA_CONSTRAINT (op, 'U'));
+  return (GET_CODE (op) == MEM
+	  && EXTRA_CONSTRAINT (op, 'U'));
 }
 
 int


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]