Comment on closed PR target/9757: Gcc should use swp instructionin ARM targets

[Arpad Beszedes <beszedes at cc dot u-szeged dot hu>]

Dear maintainers,

I would like to argue on the closed PR target/9757: Gcc should use swp 
instruction in ARM targets
http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=9757

It was closed because of the following:

    1) It's very slow on some processors, since it forces an external 
bus access even if the data is already in the cache.

My argue: if we optimize for size, speed is a trade-off. We could use a 
dedicated switch such as -fuse-swp or as part of the -Os option.

    2) It's behaviour is not defined if access is made to a MMU managed 
page that is non-cacheable/bufferable.

However,  -mcpu and -mtune can be used to specify the ARM processor. If 
that processor hasn't got a MMU, there is no such problem and this could 
also be used to enable or disable the generation of swp.

I think generating swp could be simply implemented using a peephole.

Best regards,
  Arpad Beszedes

--
******************************************************************
*  Arpad Beszedes - researcher                                   *
*                                                                *
*  Research Group on Artificial Intelligence - RGAI              *
*  Hungarian Academy of Sciences & University of Szeged, Hungary *
*  e-mail: beszedes at cc dot u-szeged dot hu                               *
*  web: http://www.inf.u-szeged.hu/~beszedes                     *
*  tel.: (+36) 62 544145                                         *
******************************************************************