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[altivec] tidy up assembler code


This just removes some unneeded/unwanted spaces from output templates.


2002-12-29  Segher Boessenkool  <segher@koffie.nl>

	* config/rs6000/altivec.md: Remove spaces from assembler
	instruction argument lists.



*** ../../gcc-clean/gcc/config/rs6000/altivec.md	Mon Jul 29 23:05:23 2002
--- ./config/rs6000/altivec.md	Sat Dec 28 19:03:45 2002
***************
*** 520,526 ****
  		      (match_operand:V16QI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 65))]
    "TARGET_ALTIVEC"
!   "vmsumubm %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsummbm"
--- 520,526 ----
  		      (match_operand:V16QI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 65))]
    "TARGET_ALTIVEC"
!   "vmsumubm %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsummbm"
***************
*** 529,535 ****
  		      (match_operand:V16QI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 66))]
    "TARGET_ALTIVEC"
!   "vmsumubm %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumuhm"
--- 529,535 ----
  		      (match_operand:V16QI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 66))]
    "TARGET_ALTIVEC"
!   "vmsumubm %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumuhm"
***************
*** 538,544 ****
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 67))]
    "TARGET_ALTIVEC"
!   "vmsumuhm %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumshm"
--- 538,544 ----
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 67))]
    "TARGET_ALTIVEC"
!   "vmsumuhm %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumshm"
***************
*** 547,553 ****
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 68))]
    "TARGET_ALTIVEC"
!   "vmsumshm %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumuhs"
--- 547,553 ----
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:V4SI 3 "register_operand" "v")] 68))]
    "TARGET_ALTIVEC"
!   "vmsumshm %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumuhs"
***************
*** 557,563 ****
                        (match_operand:V4SI 3 "register_operand" "v")] 69))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmsumuhs %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumshs"
--- 557,563 ----
                        (match_operand:V4SI 3 "register_operand" "v")] 69))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmsumuhs %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmsumshs"
***************
*** 567,573 ****
                        (match_operand:V4SI 3 "register_operand" "v")] 70))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmsumshs %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "umaxv16qi3"
--- 567,573 ----
                        (match_operand:V4SI 3 "register_operand" "v")] 70))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmsumshs %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "umaxv16qi3"
***************
*** 633,639 ****
                        (match_operand:V8HI 3 "register_operand" "v")] 71))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmhaddshs %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  (define_insn "altivec_vmhraddshs"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
--- 633,639 ----
                        (match_operand:V8HI 3 "register_operand" "v")] 71))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmhaddshs %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  (define_insn "altivec_vmhraddshs"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 642,648 ****
                        (match_operand:V8HI 3 "register_operand" "v")] 72))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmhraddshs %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  (define_insn "altivec_vmladduhm"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
--- 642,648 ----
                        (match_operand:V8HI 3 "register_operand" "v")] 72))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vmhraddshs %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  (define_insn "altivec_vmladduhm"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 650,656 ****
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:V8HI 3 "register_operand" "v")] 73))]
    "TARGET_ALTIVEC"
!   "vmladduhm %0, %1, %2, %3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmrghb"
--- 650,656 ----
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:V8HI 3 "register_operand" "v")] 73))]
    "TARGET_ALTIVEC"
!   "vmladduhm %0,%1,%2,%3"
    [(set_attr "type" "veccomplex")])
  
  (define_insn "altivec_vmrghb"
***************
*** 1298,1304 ****
    [(set (match_operand:V16QI 0 "register_operand" "=v")
          (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))]
    "TARGET_ALTIVEC"
!   "vspltisb %0, %1"
    [(set_attr "type" "vecsimple")])
  
  
--- 1298,1304 ----
    [(set (match_operand:V16QI 0 "register_operand" "=v")
          (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))]
    "TARGET_ALTIVEC"
!   "vspltisb %0,%1"
    [(set_attr "type" "vecsimple")])
  
  
***************
*** 1306,1333 ****
    [(set (match_operand:V8HI 0 "register_operand" "=v")
          (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))]
    "TARGET_ALTIVEC"
!   "vspltish %0, %1"
    [(set_attr "type" "vecsimple")])
  
  (define_insn "altivec_vspltisw"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
          (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))]
    "TARGET_ALTIVEC"
!   "vspltisw %0, %1"
    [(set_attr "type" "vecsimple")])
  
  (define_insn ""
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
    "TARGET_ALTIVEC"
!   "vspltisw %0, %1"
    [(set_attr "type" "vecsimple")])
  
  (define_insn "ftruncv4sf2"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
    	(fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
    "TARGET_ALTIVEC"
!   "vrfiz %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vperm_4si"
--- 1306,1333 ----
    [(set (match_operand:V8HI 0 "register_operand" "=v")
          (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))]
    "TARGET_ALTIVEC"
!   "vspltish %0,%1"
    [(set_attr "type" "vecsimple")])
  
  (define_insn "altivec_vspltisw"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
          (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))]
    "TARGET_ALTIVEC"
!   "vspltisw %0,%1"
    [(set_attr "type" "vecsimple")])
  
  (define_insn ""
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
    "TARGET_ALTIVEC"
!   "vspltisw %0,%1"
    [(set_attr "type" "vecsimple")])
  
  (define_insn "ftruncv4sf2"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
    	(fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
    "TARGET_ALTIVEC"
!   "vrfiz %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vperm_4si"
***************
*** 1370,1390 ****
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
    "TARGET_ALTIVEC"
!   "vrfip %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrfin"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
    "TARGET_ALTIVEC"
!   "vrfin %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrfim"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
    "TARGET_ALTIVEC"
!   "vrfim %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vcfux"
--- 1370,1390 ----
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
    "TARGET_ALTIVEC"
!   "vrfip %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrfin"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
    "TARGET_ALTIVEC"
!   "vrfin %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrfim"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
    "TARGET_ALTIVEC"
!   "vrfim %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vcfux"
***************
*** 1392,1398 ****
          (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
  	              (match_operand:QI 2 "immediate_operand" "i")] 151))]
    "TARGET_ALTIVEC"
!   "vcfux %0, %1, %2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vcfsx"
--- 1392,1398 ----
          (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
  	              (match_operand:QI 2 "immediate_operand" "i")] 151))]
    "TARGET_ALTIVEC"
!   "vcfux %0,%1,%2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vcfsx"
***************
*** 1400,1406 ****
          (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
  	              (match_operand:QI 2 "immediate_operand" "i")] 152))]
    "TARGET_ALTIVEC"
!   "vcfsx %0, %1, %2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vctuxs"
--- 1400,1406 ----
          (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
  	              (match_operand:QI 2 "immediate_operand" "i")] 152))]
    "TARGET_ALTIVEC"
!   "vcfsx %0,%1,%2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vctuxs"
***************
*** 1409,1415 ****
                        (match_operand:QI 2 "immediate_operand" "i")] 153))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vctuxs %0, %1, %2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vctsxs"
--- 1409,1415 ----
                        (match_operand:QI 2 "immediate_operand" "i")] 153))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vctuxs %0,%1,%2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vctsxs"
***************
*** 1418,1452 ****
                        (match_operand:QI 2 "immediate_operand" "i")] 154))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vctsxs %0, %1, %2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vlogefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
    "TARGET_ALTIVEC"
!   "vlogefp %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vexptefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
    "TARGET_ALTIVEC"
!   "vexptefp %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrsqrtefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
    "TARGET_ALTIVEC"
!   "vrsqrtefp %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
    "TARGET_ALTIVEC"
!   "vrefp %0, %1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vsel_4si"
--- 1418,1452 ----
                        (match_operand:QI 2 "immediate_operand" "i")] 154))
     (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
    "TARGET_ALTIVEC"
!   "vctsxs %0,%1,%2"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vlogefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
    "TARGET_ALTIVEC"
!   "vlogefp %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vexptefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
    "TARGET_ALTIVEC"
!   "vexptefp %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrsqrtefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
    "TARGET_ALTIVEC"
!   "vrsqrtefp %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vrefp"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
    "TARGET_ALTIVEC"
!   "vrefp %0,%1"
    [(set_attr "type" "vecfloat")])
  
  (define_insn "altivec_vsel_4si"
***************
*** 1491,1497 ****
  		      (match_operand:V4SI 2 "register_operand" "v")
                        (match_operand:QI 3 "immediate_operand" "i")] 163))]
    "TARGET_ALTIVEC"
!   "vsldoi %0, %1, %2, %3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vsldoi_4sf"
--- 1491,1497 ----
  		      (match_operand:V4SI 2 "register_operand" "v")
                        (match_operand:QI 3 "immediate_operand" "i")] 163))]
    "TARGET_ALTIVEC"
!   "vsldoi %0,%1,%2,%3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vsldoi_4sf"
***************
*** 1500,1506 ****
  		      (match_operand:V4SF 2 "register_operand" "v")
                        (match_operand:QI 3 "immediate_operand" "i")] 164))]
    "TARGET_ALTIVEC"
!   "vsldoi %0, %1, %2, %3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vsldoi_8hi"
--- 1500,1506 ----
  		      (match_operand:V4SF 2 "register_operand" "v")
                        (match_operand:QI 3 "immediate_operand" "i")] 164))]
    "TARGET_ALTIVEC"
!   "vsldoi %0,%1,%2,%3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vsldoi_8hi"
***************
*** 1509,1515 ****
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:QI 3 "immediate_operand" "i")] 165))]
    "TARGET_ALTIVEC"
!   "vsldoi %0, %1, %2, %3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vsldoi_16qi"
--- 1509,1515 ----
  		      (match_operand:V8HI 2 "register_operand" "v")
                        (match_operand:QI 3 "immediate_operand" "i")] 165))]
    "TARGET_ALTIVEC"
!   "vsldoi %0,%1,%2,%3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vsldoi_16qi"
***************
*** 1518,1566 ****
  		       (match_operand:V16QI 2 "register_operand" "v")
  		       (match_operand:QI 3 "immediate_operand" "i")] 166))]
    "TARGET_ALTIVEC"
!   "vsldoi %0, %1, %2, %3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupkhsb"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
    	(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
    "TARGET_ALTIVEC"
!   "vupkhsb %0, %1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupkhpx"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
    "TARGET_ALTIVEC"
!   "vupkhpx %0, %1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupkhsh"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
    "TARGET_ALTIVEC"
!   "vupkhsh %0, %1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupklsb"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
    	(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
    "TARGET_ALTIVEC"
!   "vupklsb %0, %1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupklpx"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
    "TARGET_ALTIVEC"
!   "vupklpx %0, %1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupklsh"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
    "TARGET_ALTIVEC"
!   "vupklsh %0, %1"
    [(set_attr "type" "vecperm")])
  
  ;; AltiVec predicates.
--- 1518,1566 ----
  		       (match_operand:V16QI 2 "register_operand" "v")
  		       (match_operand:QI 3 "immediate_operand" "i")] 166))]
    "TARGET_ALTIVEC"
!   "vsldoi %0,%1,%2,%3"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupkhsb"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
    	(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
    "TARGET_ALTIVEC"
!   "vupkhsb %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupkhpx"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
    "TARGET_ALTIVEC"
!   "vupkhpx %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupkhsh"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
    "TARGET_ALTIVEC"
!   "vupkhsh %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupklsb"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
    	(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
    "TARGET_ALTIVEC"
!   "vupklsb %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupklpx"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
    "TARGET_ALTIVEC"
!   "vupklpx %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vupklsh"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
    	(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
    "TARGET_ALTIVEC"
!   "vupklsh %0,%1"
    [(set_attr "type" "vecperm")])
  
  ;; AltiVec predicates.
***************
*** 1863,1869 ****
     (clobber (match_scratch:V4SF 2 "=v"))
     (clobber (match_scratch:V4SF 3 "=v"))]
    "TARGET_ALTIVEC"
!   "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3"
    [(set_attr "type" "altivec")
     (set_attr "length" "12")])
  
--- 1863,1869 ----
     (clobber (match_scratch:V4SF 2 "=v"))
     (clobber (match_scratch:V4SF 3 "=v"))]
    "TARGET_ALTIVEC"
!   "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
    [(set_attr "type" "altivec")
     (set_attr "length" "12")])



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