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[patch] gcc: Fix comment typos.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 19 Dec 2002 23:32:07 -0500 (EST)
- Subject: [patch] gcc: Fix comment typos.
Hi,
Attached is a patch to fix comment typos. Committed as obvious.
Kazu Hirata
2002-12-19 Kazu Hirata <kazu@cs.umass.edu>
* c-pretty-print.h: Fix comment typos.
* integrate.c: Likewise.
* varasm.c: Likewise.
* config/c4x/c4x.h: Likewise.
* config/c4x/c4x.md: Likewise.
* config/fr30/fr30.md: Likewise.
* config/frv/frv.c: Likewise.
* config/h8300/h8300.c: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/i386.h: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/ia64.h: Likewise.
* config/ip2k/ip2k.md: Likewise.
* config/m68hc11/m68hc11-crt0.S: Likewise.
* config/m68hc11/m68hc11.h: Likewise.
* config/m68hc11/m68hc11.md: Likewise.
* config/m68hc11/m68hc12.h: Likewise.
* config/mcore/mcore.md: Likewise.
* config/mips/mips.c: Likewise.
* config/mips/mips.md: Likewise.
* config/mmix/mmix-modes.def: Likewise.
* config/pa/pa.c: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/rs6000/rs6000.h: Likewise.
* config/rs6000/rs6000.md: Likewise.
Index: c-pretty-print.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/c-pretty-print.h,v
retrieving revision 1.5
diff -u -r1.5 c-pretty-print.h
--- c-pretty-print.h 14 Aug 2002 03:22:18 -0000 1.5
+++ c-pretty-print.h 20 Dec 2002 04:21:34 -0000
@@ -41,7 +41,7 @@
Not used yet. */
int *offset_list;
- /* These must be overriden by each of the C and C++ front-end to
+ /* These must be overridden by each of the C and C++ front-end to
reflect their understanding of syntatic productions when they differ. */
c_pretty_print_fn declaration;
c_pretty_print_fn declaration_specifiers;
@@ -141,7 +141,7 @@
/* Returns the c_pretty_printer base object of PRETTY-PRINTER. This
- macro must be overriden by any subclass of c_pretty_print_info. */
+ macro must be overridden by any subclass of c_pretty_print_info. */
#define pp_c_base(PP) (PP)
extern void pp_c_pretty_printer_init PARAMS ((c_pretty_printer));
Index: integrate.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/integrate.c,v
retrieving revision 1.207
diff -u -r1.207 integrate.c
--- integrate.c 16 Dec 2002 18:19:39 -0000 1.207
+++ integrate.c 20 Dec 2002 04:21:35 -0000
@@ -264,7 +264,7 @@
}
/* If the function has a target specific attribute attached to it,
- then we assume that we should not inline it. This can be overriden
+ then we assume that we should not inline it. This can be overridden
by the target if it defines TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P. */
if (!function_attribute_inlinable_p (fndecl))
return N_("function with target specific attribute(s) cannot be inlined");
Index: varasm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/varasm.c,v
retrieving revision 1.326
diff -u -r1.326 varasm.c
--- varasm.c 19 Dec 2002 05:18:08 -0000 1.326
+++ varasm.c 20 Dec 2002 04:21:38 -0000
@@ -5418,7 +5418,7 @@
}
/* Determine whether or not a pointer mode is valid. Assume defaults
- of ptr_mode or Pmode - can be overriden. */
+ of ptr_mode or Pmode - can be overridden. */
bool
default_valid_pointer_mode (mode)
enum machine_mode mode;
Index: config/c4x/c4x.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/c4x/c4x.h,v
retrieving revision 1.117
diff -u -r1.117 c4x.h
--- config/c4x/c4x.h 16 Dec 2002 18:21:00 -0000 1.117
+++ config/c4x/c4x.h 20 Dec 2002 04:21:40 -0000
@@ -1334,7 +1334,7 @@
#ifndef REG_OK_STRICT
-/* Nonzero if X is a hard or pseudo reg that can be used as an base. */
+/* Nonzero if X is a hard or pseudo reg that can be used as a base. */
#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
Index: config/c4x/c4x.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/c4x/c4x.md,v
retrieving revision 1.72
diff -u -r1.72 c4x.md
--- config/c4x/c4x.md 15 Sep 2002 18:24:05 -0000 1.72
+++ config/c4x/c4x.md 20 Dec 2002 04:21:42 -0000
@@ -231,7 +231,7 @@
; a new spill register.
; Note that the floating point representation of 0.0 on the C4x
-; is 0x80000000 (-2147483648). This value produces an warning
+; is 0x80000000 (-2147483648). This value produces a warning
; message on 32-bit machines about the decimal constant being so large
; that it is unsigned.
Index: config/fr30/fr30.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/fr30/fr30.md,v
retrieving revision 1.18
diff -u -r1.18 fr30.md
--- config/fr30/fr30.md 19 Dec 2002 05:18:09 -0000 1.18
+++ config/fr30/fr30.md 20 Dec 2002 04:21:42 -0000
@@ -36,7 +36,7 @@
;; Define an attribute to be used by the delay slot code.
;; An instruction by default is considered to be 'delyabable'
;; that is, it can be placed into a delay slot, but it is not
-;; itself an delyaed branch type instruction. An instruction
+;; itself a delyaed branch type instruction. An instruction
;; whoes type is 'delayed' is one which has a delay slot, and
;; an instruction whoes delay_type is 'other' is one which does
;; not have a delay slot, nor can it be placed into a delay slot.
Index: config/frv/frv.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/frv/frv.c,v
retrieving revision 1.15
diff -u -r1.15 frv.c
--- config/frv/frv.c 16 Dec 2002 18:21:09 -0000 1.15
+++ config/frv/frv.c 20 Dec 2002 04:21:46 -0000
@@ -1061,7 +1061,7 @@
case STACK_REGS_STDARG:
if (varargs_p)
{
- /* If this is a stdarg function with an non varardic argument split
+ /* If this is a stdarg function with a non varardic argument split
between registers and the stack, adjust the saved registers
downward */
last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
@@ -4791,7 +4791,7 @@
return gpr_or_int12_operand (op, mode);
}
-/* Return true if operator is an kind of relational operator */
+/* Return true if operator is a kind of relational operator. */
int
relational_operator (op, mode)
Index: config/h8300/h8300.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.c,v
retrieving revision 1.176
diff -u -r1.176 h8300.c
--- config/h8300/h8300.c 20 Dec 2002 04:05:14 -0000 1.176
+++ config/h8300/h8300.c 20 Dec 2002 04:21:47 -0000
@@ -667,7 +667,7 @@
}
/* Monitor epilogues are the same as interrupt function epilogues.
- Just make a note that we're in an monitor epilogue. */
+ Just make a note that we're in a monitor epilogue. */
if (monitor)
fprintf (file, ";monitor epilogue\n");
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.498
diff -u -r1.498 i386.c
--- config/i386/i386.c 19 Dec 2002 22:00:32 -0000 1.498
+++ config/i386/i386.c 20 Dec 2002 04:21:53 -0000
@@ -2414,7 +2414,7 @@
(mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
- /* Handle an hidden AL argument containing number of registers for varargs
+ /* Handle a hidden AL argument containing number of registers for varargs
x86-64 functions. For i386 ABI just return constm1_rtx to avoid
any AL settings. */
if (mode == VOIDmode)
@@ -8619,7 +8619,7 @@
}
/* Return cost of comparison done fcom + arithmetics operations on AX.
- All following functions do use number of instructions as an cost metrics.
+ All following functions do use number of instructions as a cost metrics.
In future this should be tweaked to compute bytes for optimize_size and
take into account performance of various instructions on various CPUs. */
static int
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.311
diff -u -r1.311 i386.h
--- config/i386/i386.h 19 Dec 2002 22:00:32 -0000 1.311
+++ config/i386/i386.h 20 Dec 2002 04:21:55 -0000
@@ -891,7 +891,7 @@
and are not available for the register allocator.
On the 80386, the stack pointer is such, as is the arg pointer.
- The value is an mask - bit 1 is set for fixed registers
+ The value is a mask - bit 1 is set for fixed registers
for 32bit target, while 2 is set for fixed registers for 64bit.
Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
*/
@@ -917,7 +917,7 @@
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like.
- The value is an mask - bit 1 is set for call used
+ The value is a mask - bit 1 is set for call used
for 32bit target, while 2 is set for call used for 64bit.
Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
*/
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.405
diff -u -r1.405 i386.md
--- config/i386/i386.md 16 Dec 2002 18:21:20 -0000 1.405
+++ config/i386/i386.md 20 Dec 2002 04:22:00 -0000
@@ -5320,7 +5320,7 @@
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
/* ???? We ought to handle there the 32bit case too
- - do we need new constrant? */
+ - do we need new constraint? */
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
@@ -5370,7 +5370,7 @@
if (! rtx_equal_p (operands[0], operands[1]))
abort ();
/* ???? We ought to handle there the 32bit case too
- - do we need new constrant? */
+ - do we need new constraint? */
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.200
diff -u -r1.200 ia64.c
--- config/ia64/ia64.c 19 Dec 2002 05:18:12 -0000 1.200
+++ config/ia64/ia64.c 20 Dec 2002 04:22:03 -0000
@@ -795,7 +795,7 @@
&& GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
}
-/* Return 1 if this is a comparison operator, which accepts an normal 8-bit
+/* Return 1 if this is a comparison operator, which accepts a normal 8-bit
signed immediate operand. */
int
@@ -5126,7 +5126,7 @@
return t;
}
-/* INSNS is an chain of instructions. Scan the chain, and insert stop bits
+/* INSNS is a chain of instructions. Scan the chain, and insert stop bits
as necessary to eliminate dependendencies. This function assumes that
a final instruction scheduling pass has been run which has already
inserted most of the necessary stop bits. This function only inserts
Index: config/ia64/ia64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.h,v
retrieving revision 1.136
diff -u -r1.136 ia64.h
--- config/ia64/ia64.h 16 Dec 2002 18:21:26 -0000 1.136
+++ config/ia64/ia64.h 20 Dec 2002 04:22:05 -0000
@@ -277,7 +277,7 @@
/* A C expression whose value is zero if pointers that need to be extended
from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
- they are zero-extended and negative one if there is an ptr_extend operation.
+ they are zero-extended and negative one if there is a ptr_extend operation.
You need not define this macro if the `POINTER_SIZE' is equal to the width
of `Pmode'. */
Index: config/ip2k/ip2k.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ip2k/ip2k.md,v
retrieving revision 1.3
diff -u -r1.3 ip2k.md
--- config/ip2k/ip2k.md 19 Sep 2002 13:51:24 -0000 1.3
+++ config/ip2k/ip2k.md 20 Dec 2002 04:22:07 -0000
@@ -5089,7 +5089,7 @@
;; Nop instruction.
;;
-;; We don't really want nops to appear in our code so just insert an comment.
+;; We don't really want nops to appear in our code so just insert a comment.
;;
(define_insn "nop"
[(const_int 0)]
Index: config/m68hc11/m68hc11-crt0.S
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11-crt0.S,v
retrieving revision 1.2
diff -u -r1.2 m68hc11-crt0.S
--- config/m68hc11/m68hc11-crt0.S 14 Aug 2002 07:32:52 -0000 1.2
+++ config/m68hc11/m68hc11-crt0.S 20 Dec 2002 04:22:07 -0000
@@ -74,7 +74,7 @@
.sect .install2,"ax",@progbits
;;
;; Call a specific initialization operation. The default is empty.
-;; It can be overriden by applications. It is intended to initialize
+;; It can be overridden by applications. It is intended to initialize
;; the 68hc11 registers. Function prototype is:
;;
;; int __premain(void);
Index: config/m68hc11/m68hc11.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11.h,v
retrieving revision 1.56
diff -u -r1.56 m68hc11.h
--- config/m68hc11/m68hc11.h 16 Dec 2002 18:21:29 -0000 1.56
+++ config/m68hc11/m68hc11.h 20 Dec 2002 04:22:08 -0000
@@ -47,7 +47,7 @@
#endif
/* We need to tell the linker the target elf format. Just pass an
- emulation option. This can be overriden by -Wl option of gcc. */
+ emulation option. This can be overridden by -Wl option of gcc. */
#ifndef LINK_SPEC
#define LINK_SPEC "%{m68hc12:-m m68hc12elf}%{!m68hc12:-m m68hc11elf} %{mrelax:-relax}"
#endif
Index: config/m68hc11/m68hc11.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11.md,v
retrieving revision 1.41
diff -u -r1.41 m68hc11.md
--- config/m68hc11/m68hc11.md 16 Dec 2002 18:21:29 -0000 1.41
+++ config/m68hc11/m68hc11.md 20 Dec 2002 04:22:10 -0000
@@ -6820,7 +6820,7 @@
;;;
;;; Catch an xgdx/xgdy followed by a (set D X/Y). If X/Y is dead, we don't
-;;; need to emit anything. Otherwise, we just need an copy of D to X/Y.
+;;; need to emit anything. Otherwise, we just need a copy of D to X/Y.
;;;
(define_peephole
[(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A"))
@@ -6836,7 +6836,7 @@
;;;
;;; Catch an xgdx/xgdy followed by a (set D X/Y). If X/Y is dead, we don't
-;;; need to emit anything. Otherwise, we just need an copy of D to X/Y.
+;;; need to emit anything. Otherwise, we just need a copy of D to X/Y.
;;;
(define_peephole
[(parallel [(set (reg:HI D_REGNUM) (match_operand:HI 0 "hard_reg_operand" "A"))
Index: config/m68hc11/m68hc12.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc12.h,v
retrieving revision 1.4
diff -u -r1.4 m68hc12.h
--- config/m68hc11/m68hc12.h 12 Jun 2002 03:06:18 -0000 1.4
+++ config/m68hc11/m68hc12.h 20 Dec 2002 04:22:10 -0000
@@ -25,7 +25,7 @@
#define CC1_SPEC ""
/* We need to tell the linker the target elf format. Just pass an
- emulation option. This can be overriden by -Wl option of gcc. */
+ emulation option. This can be overridden by -Wl option of gcc. */
#define LINK_SPEC "%{m68hc11:-m m68hc11elf}%{!m68hc11:-m m68hc12elf}"
#define CPP_SPEC \
Index: config/mcore/mcore.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mcore/mcore.md,v
retrieving revision 1.8
diff -u -r1.8 mcore.md
--- config/mcore/mcore.md 16 Dec 2002 18:21:35 -0000 1.8
+++ config/mcore/mcore.md 20 Dec 2002 04:22:11 -0000
@@ -150,7 +150,7 @@
;; ; This is done to allow bit field masks to fold together in combine.
;; ; The reload phase will force the immediate into a register at the
;; ; very end. This helps in some cases, but hurts in others: we'd
-;; ; really like to cse these immediates. However, there is an phase
+;; ; really like to cse these immediates. However, there is a phase
;; ; ordering problem here. cse picks up individual masks and cse's
;; ; those, but not folded masks (cse happens before combine). It's
;; ; not clear what the best solution is because we really want cse
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.242
diff -u -r1.242 mips.c
--- config/mips/mips.c 16 Dec 2002 18:21:35 -0000 1.242
+++ config/mips/mips.c 20 Dec 2002 04:22:15 -0000
@@ -5688,7 +5688,7 @@
'^' Print the name of the pic call-through register (t9 or $25).
'$' Print the name of the stack pointer register (sp or $29).
'+' Print the name of the gp register (gp or $28).
- '~' Output an branch alignment to LABEL_ALIGN(NULL). */
+ '~' Output a branch alignment to LABEL_ALIGN(NULL). */
void
print_operand (file, op, letter)
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.157
diff -u -r1.157 mips.md
--- config/mips/mips.md 16 Dec 2002 22:45:41 -0000 1.157
+++ config/mips/mips.md 20 Dec 2002 04:22:18 -0000
@@ -1282,7 +1282,7 @@
(const_int 8))
(const_int 4)])])
-;; On the mips16, we can sometimes split an subtract of a constant
+;; On the mips16, we can sometimes split a subtract of a constant
;; which is a 4 byte instruction into two adds which are both 2 byte
;; instructions. There are two cases: one where we are setting a
;; register to a register minus a constant, and one where we are
Index: config/mmix/mmix-modes.def
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mmix/mmix-modes.def,v
retrieving revision 1.2
diff -u -r1.2 mmix-modes.def
--- config/mmix/mmix-modes.def 21 Jun 2002 03:55:47 -0000 1.2
+++ config/mmix/mmix-modes.def 20 Dec 2002 04:22:18 -0000
@@ -34,7 +34,7 @@
the CMPU insn. Result values correspond to those in CCmode. */
CC (CC_UNS)
-/* The CC_FP mode is for an non-equality floating-point comparison, using
+/* The CC_FP mode is for a non-equality floating-point comparison, using
the FCMP or FCMPE insn. The result is (integer) -1 or 1 for
espectively a < b and a > b, otherwise 0. */
CC (CC_FP)
Index: config/pa/pa.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.c,v
retrieving revision 1.190
diff -u -r1.190 pa.c
--- config/pa/pa.c 19 Dec 2002 05:18:13 -0000 1.190
+++ config/pa/pa.c 20 Dec 2002 04:22:21 -0000
@@ -1458,7 +1458,7 @@
use scratch_reg to hold the address of the memory location.
The proper fix is to change PREFERRED_RELOAD_CLASS to return
- NO_REGS when presented with a const_int and an register class
+ NO_REGS when presented with a const_int and a register class
containing only FP registers. Doing so unfortunately creates
more problems than it solves. Fix this for 2.5. */
else if (fp_reg_operand (operand0, mode)
@@ -4300,7 +4300,7 @@
fputs ("\n\tnop", file);
return;
case '*':
- /* Output an nullification completer if there's nothing for the */
+ /* Output a nullification completer if there's nothing for the */
/* delay slot or nullification is requested. */
if (dbr_sequence_length () == 0 ||
(final_sequence &&
@@ -5428,7 +5428,7 @@
strcat (buf, " %2,%r1,%0");
break;
- /* All long conditionals. Note an short backward branch with an
+ /* All long conditionals. Note a short backward branch with an
unfilled delay slot is treated just like a long backward branch
with an unfilled delay slot. */
case 8:
@@ -5650,7 +5650,7 @@
strcat (buf, " %0,%1,%2");
break;
- /* All long conditionals. Note an short backward branch with an
+ /* All long conditionals. Note a short backward branch with an
unfilled delay slot is treated just like a long backward branch
with an unfilled delay slot. */
case 8:
@@ -5798,7 +5798,7 @@
strcat (buf, "{ %0,%2| %0,%%sar,%2}");
break;
- /* All long conditionals. Note an short backward branch with an
+ /* All long conditionals. Note a short backward branch with an
unfilled delay slot is treated just like a long backward branch
with an unfilled delay slot. */
case 8:
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.404
diff -u -r1.404 rs6000.c
--- config/rs6000/rs6000.c 16 Dec 2002 18:21:47 -0000 1.404
+++ config/rs6000/rs6000.c 20 Dec 2002 04:22:27 -0000
@@ -2349,7 +2349,7 @@
refers to a constant pool entry of an address (or the sum of it
plus a constant), a short (16-bit signed) constant plus a register,
the sum of two registers, or a register indirect, possibly with an
- auto-increment. For DFmode and DImode with an constant plus register,
+ auto-increment. For DFmode and DImode with a constant plus register,
we must ensure that both words are addressable or PowerPC64 with offset
word aligned.
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.238
diff -u -r1.238 rs6000.h
--- config/rs6000/rs6000.h 16 Dec 2002 18:21:47 -0000 1.238
+++ config/rs6000/rs6000.h 20 Dec 2002 04:22:29 -0000
@@ -2021,7 +2021,7 @@
refers to a constant pool entry of an address (or the sum of it
plus a constant), a short (16-bit signed) constant plus a register,
the sum of two registers, or a register indirect, possibly with an
- auto-increment. For DFmode and DImode with an constant plus register,
+ auto-increment. For DFmode and DImode with a constant plus register,
we must ensure that both words are addressable or PowerPC64 with offset
word aligned.
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.226
diff -u -r1.226 rs6000.md
--- config/rs6000/rs6000.md 19 Dec 2002 23:04:54 -0000 1.226
+++ config/rs6000/rs6000.md 20 Dec 2002 04:22:32 -0000
@@ -3306,7 +3306,7 @@
(const_int 0)))]
"")
-;; Split an logical operation that we can't do in one insn into two insns,
+;; Split a logical operation that we can't do in one insn into two insns,
;; each of which does one 16-bit part. This is used by combine.
(define_split
@@ -7980,7 +7980,7 @@
(const_int 0)))]
"")
-;; Split an logical operation that we can't do in one insn into two insns,
+;; Split a logical operation that we can't do in one insn into two insns,
;; each of which does one 16-bit part. This is used by combine.
(define_split