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Re: FRV docs
- From: Bernd Schmidt <bernds at redhat dot com>
- To: "Joseph S. Myers" <jsm28 at cam dot ac dot uk>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Sat, 7 Dec 2002 02:30:57 +0000 (GMT)
- Subject: Re: FRV docs
On Fri, 6 Dec 2002, Joseph S. Myers wrote:
> On Fri, 6 Dec 2002, Bernd Schmidt wrote:
>
> > + Register in the class ACC_REGS (@code{acc0} to @code{acc7}).
>
> @code{ACC_REGS} (and likewise below).
>
> > + 12-bit signed integer constant that is negative - i.e. in the
> > + range of -2048 to -1
>
> TeX em dash (--- not surrounded by spaces); @minus{} for minus signs; @:
> after i.e. not at end of sentence.
>
> > + @item P
> > + 12-bit signed integer constant that is greater than zero - i.e. in the
> > + range of 1 to 2047.
>
> Likewise.
Fixed.
Bernd
Index: doc/md.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/md.texi,v
retrieving revision 1.55
diff -c -p -r1.55 md.texi
*** doc/md.texi 6 Dec 2002 23:54:41 -0000 1.55
--- doc/md.texi 7 Dec 2002 02:28:39 -0000
*************** Memory operand except postincrement and
*** 1753,1818 ****
@item FRV---@file{frv.h}
@table @code
@item a
! Register in the class ACC_REGS (@code{acc0} to @code{acc7}).
@item b
! Register in the class EVEN_ACC_REGS (@code{acc0} to @code{acc7}).
@item c
! Register in the class CC_REGS (@code{fcc0} to @code{fcc3} and @code{icc0} to @code{icc3}).
@item d
! Register in the class GPR_REGS (@code{gr0} to @code{gr63}).
@item e
! Register in the class EVEN_REGS (@code{gr0} to @code{gr63}).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
@item f
! Register in the class FPR_REGS (@code{fr0} to @code{fr63}).
@item h
! Register in the class FEVEN_REGS (@code{fr0} to @code{fr63}).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
@item l
! Register in the class LR_REG (the @code{lr} register).
@item q
! Register in the class QUAD_REGS (@code{gr2} to @code{gr63}).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
@item t
! Register in the class ICC_REGS@ (@code{icc0} to @code{icc3}).
@item u
! Register in the class FCC_REGS (@code{fcc0} to @code{fcc3}).
@item v
! Register in the class ICR_REGS (@code{cc4} to @code{cc7}).
@item w
! Register in the class FCR_REGS (@code{cc0} to @code{cc3}).
@item x
! Register in the class QUAD_FPR_REGS (@code{fr0} to @code{fr63}).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
@item z
! Register in the class SPR_REGS (@code{lcr} and @code{lr}).
@item A
! Register in the class QUAD_ACC_REGS (@code{acc0} to @code{acc7}).
@item B
! Register in the class ACCG_REGS (@code{accg0} to @code{accg7}).
@item C
! Register in the class CR_REGS (@code{cc0} to @code{cc7}).
@item G
Floating point constant zero
--- 1753,1819 ----
@item FRV---@file{frv.h}
@table @code
@item a
! Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
@item b
! Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
@item c
! Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
! @code{icc0} to @code{icc3}).
@item d
! Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
@item e
! Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
@item f
! Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
@item h
! Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
@item l
! Register in the class @code{LR_REG} (the @code{lr} register).
@item q
! Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
@item t
! Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
@item u
! Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
@item v
! Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
@item w
! Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
@item x
! Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
@item z
! Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
@item A
! Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
@item B
! Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
@item C
! Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
@item G
Floating point constant zero
*************** Floating point constant zero
*** 1830,1843 ****
16-bit unsigned integer constant
@item N
! 12-bit signed integer constant that is negative - i.e. in the
! range of -2048 to -1
@item O
Constant zero
@item P
! 12-bit signed integer constant that is greater than zero - i.e. in the
range of 1 to 2047.
@end table
--- 1831,1844 ----
16-bit unsigned integer constant
@item N
! 12-bit signed integer constant that is negative---i.e.@: in the
! range of @minus{}2048 to @minus{}1
@item O
Constant zero
@item P
! 12-bit signed integer constant that is greater than zero---i.e.@: in the
range of 1 to 2047.
@end table