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Fix crash while compiling pine on x86_64
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, rth at cygnus dot com
- Date: Tue, 12 Nov 2002 14:53:32 +0100
- Subject: Fix crash while compiling pine on x86_64
Hi,
reload crashes on attempting to reload instruction of for
(set (strict_low_part (reg a)) (reg b) (reg c))
that can be reloaded by first setting strict low part of a by b and then
doing the operation, but reload can't and probably should not do that.
The attached patch ensures that all the operations have mathcing operand
0 and 1 so reloading is not needed.
Tue Nov 12 14:52:01 CET 2002 Jan Hubicka <jh@suse.cz>
* athlon.md, k6.md, pentium.md, ppro.md: Handle shift1, rotate1
* i386.md (attribute type): Add type shift1 and rotate1.
(*_slp): Rewrite to have just two operands to avoid reload problems.
Index: athlon.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/athlon.md,v
retrieving revision 1.1
diff -c -3 -p -r1.1 athlon.md
*** athlon.md 9 May 2002 23:41:37 -0000 1.1
--- athlon.md 11 Nov 2002 22:21:09 -0000
***************
*** 63,69 ****
(define_function_unit "athlon_ieu" 3 0
(and (eq_attr "cpu" "athlon")
! (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,rotate,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
1 1)
(define_function_unit "athlon_ieu" 3 0
--- 63,69 ----
(define_function_unit "athlon_ieu" 3 0
(and (eq_attr "cpu" "athlon")
! (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ishift1,rotate,rotate1,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
1 1)
(define_function_unit "athlon_ieu" 3 0
Index: i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.401
diff -c -3 -p -r1.401 i386.md
*** i386.md 31 Oct 2002 15:21:22 -0000 1.401
--- i386.md 11 Nov 2002 22:21:16 -0000
***************
*** 140,146 ****
(define_attr "type"
"other,multi,
alu,alu1,negnot,imov,imovx,lea,
! incdec,ishift,rotate,imul,idiv,
icmp,test,ibr,setcc,icmov,
push,pop,call,callv,
str,cld,
--- 140,146 ----
(define_attr "type"
"other,multi,
alu,alu1,negnot,imov,imovx,lea,
! incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
icmp,test,ibr,setcc,icmov,
push,pop,call,callv,
str,cld,
***************
*** 174,181 ****
(const_int 0)
(eq_attr "unit" "i387,sse,mmx")
(const_int 0)
! (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,imul,
! icmp,push,pop")
(symbol_ref "ix86_attr_length_immediate_default(insn,1)")
(eq_attr "type" "imov,test")
(symbol_ref "ix86_attr_length_immediate_default(insn,0)")
--- 174,181 ----
(const_int 0)
(eq_attr "unit" "i387,sse,mmx")
(const_int 0)
! (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
! imul,icmp,push,pop")
(symbol_ref "ix86_attr_length_immediate_default(insn,1)")
(eq_attr "type" "imov,test")
(symbol_ref "ix86_attr_length_immediate_default(insn,0)")
***************
*** 347,353 ****
(define_attr "imm_disp" "false,true,unknown"
(cond [(eq_attr "type" "other,multi")
(const_string "unknown")
! (and (eq_attr "type" "icmp,test,imov")
(and (match_operand 0 "memory_displacement_operand" "")
(match_operand 1 "immediate_operand" "")))
(const_string "true")
--- 347,353 ----
(define_attr "imm_disp" "false,true,unknown"
(cond [(eq_attr "type" "other,multi")
(const_string "unknown")
! (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
(and (match_operand 0 "memory_displacement_operand" "")
(match_operand 1 "immediate_operand" "")))
(const_string "true")
***************
*** 6040,6050 ****
(define_insn "*addqi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
! (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
! (match_operand:QI 2 "general_operand" "qn,qnm")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_binary_operator_ok (PLUS, QImode, operands)"
{
switch (get_attr_type (insn))
{
--- 6040,6050 ----
(define_insn "*addqi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
! (plus:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "qn,qnm")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (get_attr_type (insn))
{
***************
*** 6061,6069 ****
&& INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
! return "sub{b}\t{%2, %0|%0, %2}";
}
! return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
--- 6061,6069 ----
&& INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
! return "sub{b}\t{%1, %0|%0, %1}";
}
! return "add{b}\t{%1, %0|%0, %1}";
}
}
[(set (attr "type")
***************
*** 6605,6616 ****
(define_insn "*subqi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
! (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
! (match_operand:QI 2 "general_operand" "qn,qmn")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_binary_operator_ok (MINUS, QImode, operands)"
! "sub{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
--- 6605,6616 ----
(define_insn "*subqi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
! (minus:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "qn,qmn")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
! "sub{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
***************
*** 8067,8073 ****
(and:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qi,qmi")))
(clobber (reg:CC 17))]
! "! TARGET_PARTIAL_REG_STALL || optimize_size"
"and{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
--- 8067,8074 ----
(and:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qi,qmi")))
(clobber (reg:CC 17))]
! "(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"and{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
***************
*** 8104,8110 ****
(set (strict_low_part (match_dup 0))
(and:QI (match_dup 0) (match_dup 1)))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_match_ccmode (insn, CCNOmode)"
"and{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
--- 8105,8112 ----
(set (strict_low_part (match_dup 0))
(and:QI (match_dup 0) (match_dup 1)))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_match_ccmode (insn, CCNOmode)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"and{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
***************
*** 8474,8480 ****
(ior:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qmi,qi")))
(clobber (reg:CC 17))]
! "! TARGET_PARTIAL_REG_STALL || optimize_size"
"or{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
--- 8476,8483 ----
(ior:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qmi,qi")))
(clobber (reg:CC 17))]
! "(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"or{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
***************
*** 8500,8506 ****
(set (strict_low_part (match_dup 0))
(ior:QI (match_dup 0) (match_dup 1)))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_match_ccmode (insn, CCNOmode)"
"or{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
--- 8503,8510 ----
(set (strict_low_part (match_dup 0))
(ior:QI (match_dup 0) (match_dup 1)))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_match_ccmode (insn, CCNOmode)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"or{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
***************
*** 8849,8855 ****
(xor:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qi,qmi")))
(clobber (reg:CC 17))]
! "! TARGET_PARTIAL_REG_STALL || optimize_size"
"xor{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
--- 8853,8860 ----
(xor:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qi,qmi")))
(clobber (reg:CC 17))]
! "(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"xor{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
***************
*** 8949,8955 ****
(set (strict_low_part (match_dup 0))
(xor:QI (match_dup 0) (match_dup 1)))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
--- 8954,8961 ----
(set (strict_low_part (match_dup 0))
(xor:QI (match_dup 0) (match_dup 1)))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_match_ccmode (insn, CCNOmode)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"xor{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
***************
*** 11511,11524 ****
(define_insn "*ashrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
! (match_operand:QI 2 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
&& (! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"sar{b}\t%0"
! [(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
--- 11517,11530 ----
(define_insn "*ashrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (ashiftrt:QI (match_dup 0)
! (match_operand:QI 1 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
&& (! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"sar{b}\t%0"
! [(set_attr "type" "ishift1")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
***************
*** 11538,11552 ****
(define_insn "*ashrqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
! (match_operand:QI 2 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"@
! sar{b}\t{%2, %0|%0, %2}
! sar{b}\t{%b2, %0|%0, %b2}"
! [(set_attr "type" "ishift")
(set_attr "mode" "QI")])
;; This pattern can't accept a variable shift count, since shifts by
--- 11544,11558 ----
(define_insn "*ashrqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (ashiftrt:QI (match_dup 0)
! (match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
! sar{b}\t{%1, %0|%0, %1}
! sar{b}\t{%b1, %0|%0, %b1}"
! [(set_attr "type" "ishift1")
(set_attr "mode" "QI")])
;; This pattern can't accept a variable shift count, since shifts by
***************
*** 11930,11943 ****
(define_insn "*lshrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
! (match_operand:QI 2 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{b}\t%0"
! [(set_attr "type" "ishift")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
--- 11936,11948 ----
(define_insn "*lshrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (lshiftrt:QI (match_dup 0)
! (match_operand:QI 1 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{b}\t%0"
! [(set_attr "type" "ishift1")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
***************
*** 11957,11971 ****
(define_insn "*lshrqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
! (match_operand:QI 2 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"@
! shr{b}\t{%2, %0|%0, %2}
! shr{b}\t{%b2, %0|%0, %b2}"
! [(set_attr "type" "ishift")
(set_attr "mode" "QI")])
;; This pattern can't accept a variable shift count, since shifts by
--- 11962,11976 ----
(define_insn "*lshrqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (lshiftrt:QI (match_dup 0)
! (match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
! shr{b}\t{%1, %0|%0, %1}
! shr{b}\t{%b1, %0|%0, %b1}"
! [(set_attr "type" "ishift1")
(set_attr "mode" "QI")])
;; This pattern can't accept a variable shift count, since shifts by
***************
*** 12145,12158 ****
(define_insn "*rotlqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
! (match_operand:QI 2 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && ix86_binary_operator_ok (ROTATE, QImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{b}\t%0"
! [(set_attr "type" "rotate")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
--- 12150,12162 ----
(define_insn "*rotlqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (rotate:QI (match_dup 0)
! (match_operand:QI 1 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{b}\t%0"
! [(set_attr "type" "rotate1")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
***************
*** 12174,12188 ****
(define_insn "*rotlqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
! (match_operand:QI 2 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_binary_operator_ok (ROTATE, QImode, operands)"
"@
! rol{b}\t{%2, %0|%0, %2}
! rol{b}\t{%b2, %0|%0, %b2}"
! [(set_attr "type" "rotate")
(set_attr "mode" "QI")])
(define_insn "*rotlqi3_1"
--- 12178,12192 ----
(define_insn "*rotlqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (rotate:QI (match_dup 0)
! (match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
! rol{b}\t{%1, %0|%0, %1}
! rol{b}\t{%b1, %0|%0, %b1}"
! [(set_attr "type" "rotate1")
(set_attr "mode" "QI")])
(define_insn "*rotlqi3_1"
***************
*** 12351,12364 ****
(define_insn "*rotrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
! (match_operand:QI 2 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && ix86_binary_operator_ok (ROTATERT, QImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{b}\t%0"
! [(set_attr "type" "rotate")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
--- 12355,12367 ----
(define_insn "*rotrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
! (rotatert:QI (match_dup 0)
! (match_operand:QI 1 "const_int_1_operand" "")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{b}\t%0"
! [(set_attr "type" "rotate1")
(set (attr "length")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "2")
***************
*** 12378,12392 ****
(define_insn "*rotrqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
! (match_operand:QI 2 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && ix86_binary_operator_ok (ROTATERT, QImode, operands)"
"@
! ror{b}\t{%2, %0|%0, %2}
! ror{b}\t{%b2, %0|%0, %b2}"
! [(set_attr "type" "rotate")
(set_attr "mode" "QI")])
;; Bit set / bit test instructions
--- 12381,12395 ----
(define_insn "*rotrqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
! (rotatert:QI (match_dup 0)
! (match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC 17))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
! && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
! ror{b}\t{%1, %0|%0, %1}
! ror{b}\t{%b1, %0|%0, %b1}"
! [(set_attr "type" "rotate1")
(set_attr "mode" "QI")])
;; Bit set / bit test instructions
Index: k6.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/k6.md,v
retrieving revision 1.1
diff -c -3 -p -r1.1 k6.md
*** k6.md 9 May 2002 23:41:39 -0000 1.1
--- k6.md 11 Nov 2002 22:21:16 -0000
***************
*** 42,48 ****
;; Shift instructions and certain arithmetic are issued only to X pipe.
(define_function_unit "k6_alux" 1 0
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "ishift,rotate,alu1,negnot,cld"))
1 1)
;; The QI mode arithmetic is issued to X pipe only.
--- 42,48 ----
;; Shift instructions and certain arithmetic are issued only to X pipe.
(define_function_unit "k6_alux" 1 0
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld"))
1 1)
;; The QI mode arithmetic is issued to X pipe only.
***************
*** 54,60 ****
(define_function_unit "k6_alu" 2 0
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "ishift,rotate,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
1 1)
(define_function_unit "k6_alu" 2 0
--- 54,60 ----
(define_function_unit "k6_alu" 2 0
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
1 1)
(define_function_unit "k6_alu" 2 0
Index: pentium.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/pentium.md,v
retrieving revision 1.3
diff -c -3 -p -r1.3 pentium.md
*** pentium.md 19 Sep 2002 13:51:23 -0000 1.3
--- pentium.md 11 Nov 2002 22:21:16 -0000
***************
*** 53,58 ****
--- 53,64 ----
(and (eq_attr "type" "rotate")
(match_operand 2 "const_int_1_operand" ""))
(const_string "pu")
+ (and (eq_attr "type" "ishift1")
+ (match_operand 1 "const_int_operand" ""))
+ (const_string "pu")
+ (and (eq_attr "type" "rotate1")
+ (match_operand 1 "const_int_1_operand" ""))
+ (const_string "pu")
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand" ""))
(const_string "pv")
Index: ppro.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/ppro.md,v
retrieving revision 1.1
diff -c -3 -p -r1.1 ppro.md
*** ppro.md 9 May 2002 23:41:39 -0000 1.1
--- ppro.md 11 Nov 2002 22:21:16 -0000
***************
*** 60,66 ****
(define_function_unit "ppro_p0" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "ishift,rotate,lea,ibr,cld"))
1 1)
(define_function_unit "ppro_p0" 1 0
--- 60,66 ----
(define_function_unit "ppro_p0" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "ishift,rotate,ishift1,rotate1,lea,ibr,cld"))
1 1)
(define_function_unit "ppro_p0" 1 0