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Re: PowerPC PIC code addressibility tweak
- From: Segher Boessenkool <segher at koffie dot nl>
- To: David Edelsohn <dje at watson dot ibm dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Sat, 02 Nov 2002 02:17:23 +0100
- Subject: Re: PowerPC PIC code addressibility tweak
- References: <200211011526.KAA29924@makai.watson.ibm.com>
David Edelsohn wrote:
>
> >>>>> Segher Boessenkool writes:
>
> Segher> What document did you take this from? I could only find this in the
> Segher> Book E and in the 7450 UM, but both specifically say this is special
> Segher> cased only for
>
> Segher> bcl 20,31,$+4
>
> Segher> so your second patch won't help (as it uses $+8 instead).
>
> The recommendation is in the PowerPC Microprocessor Family
> Programming Environments book. The example is for $+4, but the effect is
> not pushing the link register stack. At worst, the new instruction is no
> worse than the former one.
That's true, of course.
Another idea: why not generate something like
bl $+4 ; blr
(and do something smart for the second case).
That would leave the return stack intact always (but might be bad for
branch prediction?)
Segher