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SSE fix 31 - 64bit movmaskdqu pattern
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, rth at cygnus dot com
- Date: Sun, 27 Oct 2002 23:32:20 +0100
- Subject: SSE fix 31 - 64bit movmaskdqu pattern
Hi,
another pattern having address operand unwound, so we need two variants.
Sun Oct 27 23:30:24 CET 2002 Jan Hubicka <jh@suse.cz>
* i386.c (ix86_expand_builtin): Use sse2_maskmovdqu_rex64.
* i386.md (sse2_maskmovdqu_rex64): New pattern
Index: i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.486
diff -c -3 -p -r1.486 i386.c
*** i386.c 24 Oct 2002 22:36:25 -0000 1.486
--- i386.c 27 Oct 2002 09:19:18 -0000
*************** ix86_expand_builtin (exp, target, subtar
*** 13145,13151 ****
case IX86_BUILTIN_MASKMOVDQU:
icode = (fcode == IX86_BUILTIN_MASKMOVQ
? (TARGET_64BIT ? CODE_FOR_mmx_maskmovq_rex : CODE_FOR_mmx_maskmovq)
! : CODE_FOR_sse2_maskmovdqu);
/* Note the arg order is different from the operand order. */
arg1 = TREE_VALUE (arglist);
arg2 = TREE_VALUE (TREE_CHAIN (arglist));
--- 13145,13152 ----
case IX86_BUILTIN_MASKMOVDQU:
icode = (fcode == IX86_BUILTIN_MASKMOVQ
? (TARGET_64BIT ? CODE_FOR_mmx_maskmovq_rex : CODE_FOR_mmx_maskmovq)
! : (TARGET_64BIT ? CODE_FOR_sse2_maskmovdqu_rex64
! : CODE_FOR_sse2_maskmovdqu));
/* Note the arg order is different from the operand order. */
arg1 = TREE_VALUE (arglist);
arg2 = TREE_VALUE (TREE_CHAIN (arglist));
Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.399
diff -c -3 -p -r1.399 i386.md
*** i386.md 23 Oct 2002 01:06:40 -0000 1.399
--- i386.md 27 Oct 2002 09:19:32 -0000
***************
*** 20552,20557 ****
--- 20552,20568 ----
[(set_attr "type" "ssecvt")
(set_attr "mode" "TI")])
+ (define_insn "sse2_maskmovdqu_rex64"
+ [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
+ (match_operand:V16QI 2 "register_operand" "x")]
+ UNSPEC_MASKMOV))]
+ "TARGET_SSE2"
+ ;; @@@ check ordering of operands in intel/nonintel syntax
+ "maskmovdqu\t{%2, %1|%1, %2}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "mode" "TI")])
+
(define_insn "sse2_movntv2df"
[(set (match_operand:V2DF 0 "memory_operand" "=m")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]