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Another patch to the mips64vr-elf config.
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: echristo at redhat dot com
- Date: 16 Oct 2002 12:11:34 +0100
- Subject: Another patch to the mips64vr-elf config.
The mips64vr-elf config assumes that -msoft-float is automatically
selected for vr4100 and vr4120 targets. It would make sense to
extend the same logic to other soft-float targets, but I'll just
stick to the ones I know.
Tested on mips64vr-elf. OK for mainline?
Richard
* config/mips/mips.c (override_options): Make -msoft-float the
default for vr4100 and vr4120 targets.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.236
diff -c -d -p -r1.236 mips.c
*** config/mips/mips.c 14 Oct 2002 19:53:25 -0000 1.236
--- config/mips/mips.c 16 Oct 2002 08:45:07 -0000
*************** override_options ()
*** 5220,5225 ****
--- 5220,5247 ----
target_flags &= ~MASK_LONG64;
}
+ if ((target_flags_explicit & MASK_SOFT_FLOAT) == 0)
+ {
+ /* If the user didn't say whether an FPU was available, and
+ we have a processor without an FPU, assume -msoft-float.
+ The idea is that:
+
+ - Any configuration can generate code for the processors
+ listed here without an explicit FPU switch.
+
+ - Configurations which default to a processor listed here can
+ generate code for hard-float processors without an FPU switch,
+ provided they don't include MASK_SOFT_FLOAT in the default
+ target flags. */
+ switch ((int) mips_arch)
+ {
+ case PROCESSOR_R4100:
+ case PROCESSOR_R4120:
+ target_flags |= MASK_SOFT_FLOAT;
+ break;
+ }
+ }
+
if (mips_abi != ABI_32 && mips_abi != ABI_O64)
flag_pcc_struct_return = 0;