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Re: [patch] new cpu sr71k
- From: Eric Christopher <echristo at redhat dot com>
- To: cgd at broadcom dot com
- Cc: gcc-patches at gcc dot gnu dot org
- Date: 13 Sep 2002 12:19:47 -0700
- Subject: Re: [patch] new cpu sr71k
- References: <1029483408.18362.73.camel@hex><mailpost.1029483433.19119@news-sj1-1> <yov5y9a594x5.fsf@broadcom.com>
On Fri, 2002-09-13 at 10:26, cgd@broadcom.com wrote:
> So, e-mail from somebody gave me some cause to look further at this
> patch:
>
> At Fri, 16 Aug 2002 07:37:13 +0000 (UTC), "Eric Christopher" wrote:
> > -#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
> > +#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
> > + && !TARGET_SR71K \
> > + && !TARGET_MIPS16)
>
> I don't understand why that's the right thing.
>
> If SR71K doesn't support branch-likely instructions at all or they are
> buggy on that processor, a conditional should be added
> ISA_HAS_BRANCHLIKELY.
>
>
> (It occurs to me that I should add TUNE_SB1 into the code in mips.c,
> to express a preference regardless of ISA_*.)
>
>
> thoughts?
Yes yes... :) It was part of an old patch that I forgot to switch
over...
-eric
--
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