Re: automaton based scheduler documentation

[Aldy Hernandez <aldyh at redhat dot com>]

>>>>> "Joern" == Joern Rennecke <joern.rennecke@superh.com> writes:

 > -To achieve better productivity most modern processors
 > +To achieve better performance most modern processors

To achieve better performance COMMA most modern processors

 > -instruction scheduler.  For better solution of this problem, the
 > +instruction scheduler.  For a better solution of this problem, the

instruction scheduler.  For a better solution TO this problem, the

 >  has two ways to describe processor parallelism.  The first one is old
 > -and originated from instruction scheduler written by Michael Tiemann
 > +and originated from the instruction scheduler written by Michael Tiemann
 >  and described in the first subsequent section.  The second one was

The above all sounds choppy, perhaps:

"There are two ways to describe processor parallelism.  GCC implements
two alternatives, both described below.  The first method is desribed
in the next section.  The second, and preferred method, is based on a
functional unit description.......

 > -generated from the old description.  Also its speed is not depended on
 > +generated from the old description.  Also its speed is not dependent on

generated from the old description.  FURTHERMORE COMMA its speed is
not dependent on

 > +the automaton based pipeline description, the given latency time is used
 >  only for true dependencies.  The cost of anti-dependencies is always

not "is used only" but "is only used".

 >  is negative, the cost is considered to be zero).  You always can
 > -change the default costs for any description by using target hook
 > +change the default costs for any description by using the target hook

not "always can" but "can always".

 > -@var{regexp} is a string describing reservation of the cpu functional
 > +@var{regexp} is a string describing the reservation of the cpu functional

"of the cpu's functional"

 >  results are ready in 3 cycles.  There is also additional one cycle

"a ONE cycle"

 > -delay in the usage by integer insns of result produced by floating
 > +delay in the usage by integer insns of results produced by
 > floating

The above sentence should be rewritten.

 > -The automaton based pipeline hazard recognizer speed is not depended
 > +The automaton based pipeline hazard recognizer speed is not dependent
 >  on processor complexity.

"In an automaton based pipeline hazard recognizer, speed is not..."