Re: [RFC] PowerPC DFA description

[Daniel Egger <degger at fhm dot edu>]

Am Mit, 2002-05-29 um 21.54 schrieb David Edelsohn:

> 	Appended is a first attempt at a DFA description for PowerPC.
> This is based on the DFA description originally developed by Red Hat for
> an earlier version of GCC.  I updated it to include processors which were
> not present when the original decription was developed and fixed various
> errors I found while verifying the original scheduling description
> translation.

I had a look at it and can say that it's nice work so far. I attached a
patch to add altivec support for the 7400 also.

I also have two questions if you don't mind. :)

1) Not all instructions in an unit, not even in an insns group have the
same latency. How can we model that?
2) Since we care about issue units don't we also have to about
completion units and alike?

-- 
Servus,
       Daniel
--- automaton	Wed May 29 23:11:54 2002
+++ automaton-new	Thu May 30 00:02:14 2002
@@ -3,6 +3,7 @@
 (define_automaton "iu3_other")
 (define_automaton "fpu2_other")
 (define_automaton "vec_alu")
+(define_automaton "vec_perm")
 (define_automaton "mciu_other,mciu_idiv")
 (define_automaton "dispatch")
 (define_automaton "vdisp")
@@ -44,6 +45,8 @@
 (define_cpu_unit "vec_float" "vec_alu")
 (define_cpu_unit "vec_permute" "vec_alu")
 
+(define_cpu_unit "vec_permute2" "vec_perm")
+
 ;; Branch prediction unit (BPU)
 (define_cpu_unit "bpu" "other")
 
@@ -867,6 +870,7 @@
 ;; Max issue 3 insns/clock cycle (includes 1 branch)
 ;; In-order execution
 
+;; Additionally the PPC7400 sports a Vector Permute Unit and a Vector ALU
 
 ;; The PPC750 user's manual recommends that to reduce branch mispredictions,
 ;; the insn that sets CR bits should be separated from the branch insn
@@ -964,6 +968,26 @@
   (and (eq_attr "type" "jmpreg,branch")
        (eq_attr "cpu" "ppc750,ppc7400"))
   "nothing,bpu")
+
+(define_insn_reservation "ppc7400-vecsimple" 1
+  (and (eq_attr "type" "vecsimple,veccmp")
+       (eq_attr "cpu" "ppc7400"))
+  "ppc750_du,vec_simple")
+
+(define_insn_reservation "ppc7400-veccomplex" 4
+  (and (eq_attr "type" "veccomplex")
+       (eq_attr "cpu" "ppc7400"))
+  "ppc750_du,vec_complex")
+
+(define_insn_reservation "ppc7400-vecfloat" 4
+  (and (eq_attr "type" "vecfloat")
+       (eq_attr "cpu" "ppc7400"))
+  "ppc750_du,vec_float")
+
+(define_insn_reservation "ppc7400-vecperm" 2
+  (and (eq_attr "type" "vecperm")
+       (eq_attr "cpu" "ppc7400"))
+  "ppc750_du,vec_permute2")
 
 
 ;; PPC7450  32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC