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altivec is not the only simd arch
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org, dje at watson dot ibm dot com
- Date: Mon, 20 May 2002 12:10:02 +1000
- Subject: altivec is not the only simd arch
hello.
i just noticed that there are a few places scattered throughout
that we wrongly assume vectors are always altivec vectors. this isn't
necessarily so, especially since i'm working on another non-altivec
simd architecture for the powerpc ;-).
also, i have some in-the-works patches for allowing backends to use
the vector modes (V4SI, V2SI, etc) without actually having hardware
support for them.
so... assuming altivec is the only simd architecture is very bad.
obvious fix. committed to mainline.
2002-05-19 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.h (FUNCTION_VALUE): Only return vectors in
an altivec register if TARGET_ALTIVEC.
* config/rs600/rs6000.c (rs6000_emit_move): Change VECTOR_MODE_P
to ALTIVEC_VECTOR_MODE.
(rs6000_va_arg): Only vectors of type AltiVec are 16 byte aligned.
(rs6000_va_arg): Vectors may go in registers if they are not
altivec vectors.
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.202
diff -c -p -r1.202 rs6000.h
*** config/rs6000/rs6000.h 15 May 2002 23:45:52 -0000 1.202
--- config/rs6000/rs6000.h 20 May 2002 02:08:53 -0000
*************** typedef struct rs6000_stack {
*** 1460,1466 ****
&& TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
|| POINTER_TYPE_P (VALTYPE) \
? word_mode : TYPE_MODE (VALTYPE), \
! TREE_CODE (VALTYPE) == VECTOR_TYPE ? ALTIVEC_ARG_RETURN \
: TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
? FP_ARG_RETURN : GP_ARG_RETURN)
--- 1460,1467 ----
&& TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
|| POINTER_TYPE_P (VALTYPE) \
? word_mode : TYPE_MODE (VALTYPE), \
! TREE_CODE (VALTYPE) == VECTOR_TYPE \
! && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \
: TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
? FP_ARG_RETURN : GP_ARG_RETURN)
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.317
diff -c -p -r1.317 rs6000.c
*** config/rs6000/rs6000.c 13 May 2002 04:50:15 -0000 1.317
--- config/rs6000/rs6000.c 20 May 2002 02:08:59 -0000
*************** rs6000_emit_move (dest, source, mode)
*** 2300,2306 ****
/* Handle the case where reload calls us with an invalid address;
and the case of CONSTANT_P_RTX. */
! if (!VECTOR_MODE_P (mode)
&& (! general_operand (operands[1], mode)
|| ! nonimmediate_operand (operands[0], mode)
|| GET_CODE (operands[1]) == CONSTANT_P_RTX))
--- 2300,2306 ----
/* Handle the case where reload calls us with an invalid address;
and the case of CONSTANT_P_RTX. */
! if (!ALTIVEC_VECTOR_MODE (mode)
&& (! general_operand (operands[1], mode)
|| ! nonimmediate_operand (operands[0], mode)
|| GET_CODE (operands[1]) == CONSTANT_P_RTX))
*************** rs6000_va_arg (valist, type)
*** 3210,3217 ****
lab_over = gen_label_rtx ();
addr_rtx = gen_reg_rtx (Pmode);
! /* Vectors never go in registers. */
! if (TREE_CODE (type) != VECTOR_TYPE)
{
TREE_THIS_VOLATILE (reg) = 1;
emit_cmp_and_jump_insns
--- 3210,3217 ----
lab_over = gen_label_rtx ();
addr_rtx = gen_reg_rtx (Pmode);
! /* AltiVec vectors never go in registers. */
! if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
{
TREE_THIS_VOLATILE (reg) = 1;
emit_cmp_and_jump_insns
*************** rs6000_va_arg (valist, type)
*** 3265,3271 ****
All AltiVec vectors go in the overflow area. So in the AltiVec
case we need to get the vectors from the overflow area, but
remember where the GPRs and FPRs are. */
! if (n_reg > 1 && TREE_CODE (type) != VECTOR_TYPE)
{
t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
TREE_SIDE_EFFECTS (t) = 1;
--- 3265,3272 ----
All AltiVec vectors go in the overflow area. So in the AltiVec
case we need to get the vectors from the overflow area, but
remember where the GPRs and FPRs are. */
! if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
! || !TARGET_ALTIVEC))
{
t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
TREE_SIDE_EFFECTS (t) = 1;
*************** rs6000_va_arg (valist, type)
*** 3279,3286 ****
{
int align;
! /* Vectors are 16 byte aligned. */
! if (TREE_CODE (type) == VECTOR_TYPE)
align = 15;
else
align = 7;
--- 3280,3287 ----
{
int align;
! /* AltiVec vectors are 16 byte aligned. */
! if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
align = 15;
else
align = 7;