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More web page updates
- From: law at redhat dot com
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 06 May 2002 14:40:10 -0600
- Subject: More web page updates
- Reply-to: law at redhat dot com
Mention Aldy's altivec work.
More info on DFA scheduler on a new page.
Index: index.html
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*************** and automated testers</a> to maintain an
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<dl>
+ <dt><b>May 5, 2002</b></dt>
+ <dd>
+ Aldy Hernandez, of <a href="http://www.redhat.com/";>Red Hat, Inc</a>
+ has contributed extensions to the PowerPC port supporting the AltiVec
+ programming model (SIMD). The support, though presently useful, is
+ experimental and is expected to stabilize for 3.2. The support is
+ written to conform to Motorola's AltiVec specs.
+ </dd>
+
<dt><b>May 2, 2002</b></dt>
<dd>
<a href="http://www.hp.com/";>HP</a> and <a
*************** will sponsor Mark Mitchell's work as GCC
*** 177,188 ****
<dt><b>April 30, 2002</b></dt>
<dd>
! Vladimir Makarov, of <a href="http://www.redhat.com/";>Red Hat</a>, has
! contributed a new scheme for describing processor pipelines (commonly
! referred to as the DFA scheduler). This
! new scheme can model certain pipeline architectures more
! effectively than the old scheme, which in turn can improve the code
! generated by the compiler.
</dd>
<dt><b>April 15, 2002</b></dt>
--- 186,194 ----
<dt><b>April 30, 2002</b></dt>
<dd>
! Vladimir Makarov, of <a href="http://www.redhat.com/";>Red Hat, Inc</a>, has
! contributed a new scheme for describing processor pipelines, commonly
! referred to as the <a href="news/dfa.html"> DFA scheduler.</a>
</dd>
<dt><b>April 15, 2002</b></dt>
Index: news/dfa.html
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+ <html>
+
+ <head>
+ <title>DFA Scheduler</title>
+ </head>
+
+ <body>
+ <h1>DFA Scheduler</h1>
+
+ <p>Original April 30, 2002.
+ <br>Last Updated May 5, 2002</p>
+
+ <p>We are pleased to announce that Vladimir Makarov, of <a
+ href="http://www.redhat.com";>Red Hat</a>, has contributed support
+ for using Deterministic Finite Automata (DFA) to describe structural
+ hazards in processor pipelines to the instruction scheduler. This
+ work is based on literature from various sources, including, but not
+ limited to:
+ <ul>
+ <li> Efficient Instruction Scheduling Using Finite State Automata.
+ Bala and Rubin, MICRO-28.
+ <li> Employing Finite State Automata for Resource Scheduling.
+ Muller, MICRO-26.
+ <li> Detecting Pipeline Structural Hazards Quickly.
+ Proebsting and Fraser, POPL '94.
+ </ul>
+
+
+ <p>The instruction scheduler is responsible for reordering instructions
+ based on data, control and structural hazards to improve performance.
+ The current scheduler models the pipeline of the target processor using
+ information such as the number and type of functional units as well
+ as the latency and throughput of those units. An instruction is scheduled
+ to execute when it is the highest priority instruction with no pending
+ hazards. More accurate modeling of the processor pipeline can ultimately
+ result in better performance of the generated code.
+
+ <p>The existing model works well, but has limitations. For example,
describing
+ processors with similar, but not 100% identical pipelines is difficult
+ at best. While these pipelines can be modeled, it is extremely
non-intuitive.
+ Consider <a href="http://gcc.gnu.org/ml/gcc/2002-05/msg00199.html";>this
message
+ from the GCC mailing lists.</a> As others pointed out later, the
+ pipeline description for the PPro/P2/P3 pipelines is purposefully inaccurate
+ and marks instructions which only use P0 as also using P01 to avoid
+ over-subscribing the P01 units.
+
+ <p>The DFA model can also accurately describe resources that are used at
+ different times during the overall lifetime of an instruction. So,
+ for example, using a DFA description we could model a hazard caused
+ by two classes of instructions retiring at the same time in an out of
+ order execution machine.
+
+ <p>The DFA model allows for extremely fast recognition of structural
+ hazards. This allows the compiler to efficiently try multiple schedules
+ to maximize issue throughput for example. This can be particularly
+ important on large superscalar, VLIW, and EPIC architectures.
+
+ <p>The DFA model can accurately describe packing of multiple operations
+ into instruction words. Thus it can be used to handle creation of
+ VLIW and EPIC instruction words.
+
+ <p>By building both the DFA an the reverse DFA it is possible to build a
+ scheduler which can verify replacement of instructions does not
+ introduce any new hazards or lengthen a schedule. The ability to
+ perform these verifications can be extremely helpful in building
+ software pipeliners or in building schedules for VLIW processors.
+
+
+ <p>We would like to thank the following individual contributors who
+ have worked on the DFA code or on processor descriptions.
+ <ul>
+ <li> Vladimir Makarov of Red Hat for building the base DFA implementation.
+ <li> Naveen Sharma of HCL Technologies for building a DFA description for
+ the SH4.
+ <li> Richard Henderson of Red Hat for DFA descriptions for the Alpha
processor
+ family.
+ <li> Jeff Law of Red Hat for DFA descriptions for the HP-PA processor
family.
+ <li> David Miller of Red Hat for DFA descriptions for the Sparc processor
+ family.
+ <li> Other contributors will be added here as new DFA descriptions are
+ integrated. DFA descriptions exist in one for or another for
+ various members of the IA-32, MIPS, PPC, FRV, IA-64 and other
+ processor families.
+ </ul>
+
+ </body>
+ </html>