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Re: IA64 HP-UX Optimization patch
- From: Steve Ellcey <sje at cup dot hp dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: rth at redhat dot com
- Date: Fri, 29 Mar 2002 07:51:17 -0800 (PST)
- Subject: Re: IA64 HP-UX Optimization patch
> You need to modify PREDICATE_CODES as well. You should have
> gotten warnings from genrecog about this.
>
> r~
Whoops, I had that, it just got dropped from the patch. Here it is
again with ia64.h included to update PREDICATE_CODES.
Steve Ellcey
sje@cup.hp.com
2002-03-28 Steve Ellcey <sje@cup.hp.com>
* gcc/config/ia64.md (*ptr_extend_plus_1, *ptr_extend_plus_2):
New optimized versions of ptr_extend.
* gcc/config/ia64.c (basereg_operand): New predicate used in
above instructions.
* gcc/config/ia64-protos.h (basereg_operand): Ditto.
* gcc/config/ia64.h (basreg_operand): Add to PREDICATE_CODES
*** gcc.orig/gcc/config/ia64/ia64.md Thu Mar 28 08:12:07 2002
--- gcc/gcc/config/ia64/ia64.md Thu Mar 28 09:11:04 2002
***************
*** 5304,5309 ****
--- 5304,5332 ----
[(set_attr "itanium_class" "ialu")])
;;
+ ;; Optimizations for ptr_extend
+
+ (define_insn "*ptr_extend_plus_1"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (unspec:DI
+ [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
+ (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
+ 24))]
+ ""
+ "addp4 %0 = %2, %1"
+ [(set_attr "itanium_class" "ialu")])
+
+ (define_insn "*ptr_extend_plus_2"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (unspec:DI
+ [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
+ (match_operand:SI 2 "basereg_operand" "r"))]
+ 24))]
+ ""
+ "addp4 %0 = %1, %2"
+ [(set_attr "itanium_class" "ialu")])
+
+ ;;
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling
(define_insn "prologue_use"
*** gcc.orig/gcc/config/ia64/ia64.c Thu Mar 28 08:12:10 2002
--- gcc/gcc/config/ia64/ia64.c Thu Mar 28 08:47:47 2002
*************** tfreg_or_fp01_operand (op, mode)
*** 864,869 ****
--- 864,884 ----
return 0;
return fr_reg_or_fp01_operand (op, mode);
}
+
+ /* Return 1 if OP is valid as a base register in a reg + offset address. */
+
+ int
+ basereg_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+ {
+ /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
+ checks from pa.c basereg_operand as well? Seems to be OK without them
+ in test runs. */
+
+ return (register_operand (op, mode) &&
+ REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
+ }
/* Return 1 if the operands of a move are ok. */
*** gcc.orig/gcc/config/ia64/ia64-protos.h Thu Mar 28 08:43:32 2002
--- gcc/gcc/config/ia64/ia64-protos.h Thu Mar 28 08:44:02 2002
*************** extern int ar_pfs_reg_operand PARAMS((rt
*** 66,71 ****
--- 66,72 ----
extern int general_tfmode_operand PARAMS((rtx, enum machine_mode));
extern int destination_tfmode_operand PARAMS((rtx, enum machine_mode));
extern int tfreg_or_fp01_operand PARAMS((rtx, enum machine_mode));
+ extern int basereg_operand PARAMS((rtx, enum machine_mode));
extern int ia64_move_ok PARAMS((rtx, rtx));
extern int ia64_depz_field_mask PARAMS((rtx, rtx));
*** gcc.orig/gcc/config/ia64/ia64.h Fri Mar 29 07:43:08 2002
--- gcc/gcc/config/ia64/ia64.h Fri Mar 29 07:43:38 2002
*************** do { \
*** 2351,2357 ****
{ "ar_pfs_reg_operand", {REG}}, \
{ "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
{ "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
! { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}},
/* An alias for a machine mode name. This is the machine mode that elements of
a jump-table should have. */
--- 2351,2358 ----
{ "ar_pfs_reg_operand", {REG}}, \
{ "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
{ "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
! { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
! { "basereg_operand", {SUBREG, REG}},
/* An alias for a machine mode name. This is the machine mode that elements of
a jump-table should have. */