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Fix for ARM big-endian woes
- From: Nick Clifton <nickc at cambridge dot redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 18 Mar 2002 10:20:54 +0000
- Subject: Fix for ARM big-endian woes
Hi Guys,
The big-endian multilib for ARM based toolchains has suffered from
bit rot of late. But fortunately Bernd Schmidt was able to fix the
problems and I am applying patch (attached below) to remedy the
situation.
Cheers
Nick
2002-03-18 Bernd Schmidt <bernds@redhat.com>
* config/arm/arm.c (arm_gen_movstrqi): Use gen_lowpart instead
of gen_rtx_SUBREG.
(arm_reload_out_hi): Use gen_lowpart instead of
gen_rtx_SUBREG to access QImode components.
* config/arm/arm.md: Disable zero_extend split for QImode
subregs in BIG_ENDIAN mode.
(storehi_bigend): Match use of least significant byte.
(storeinthi): Remove extraneous SUBREG.
Add missing construction of operands[2].
(movhi): Use gen_lowpart in place of gen_rtx_SUBREG.
(movqi): Use gen_lowpart in place of gen_rtx_SUBREG.
Replace gen_rtx (SUBREG) with gen_rtx_SUBREG.
Index: gcc/config/arm/arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.198
diff -c -3 -p -w -r1.198 arm.c
*** arm.c 2002/03/14 15:09:13 1.198
--- arm.c 2002/03/18 10:03:32
*************** arm_gen_movstrqi (operands)
*** 4544,4550 ****
RTX_UNCHANGING_P (mem) = dst_unchanging_p;
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
! emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
if (--last_bytes)
{
--- 4544,4550 ----
RTX_UNCHANGING_P (mem) = dst_unchanging_p;
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
! emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
if (--last_bytes)
{
*************** arm_gen_movstrqi (operands)
*** 4563,4569 ****
RTX_UNCHANGING_P (mem) = dst_unchanging_p;
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
! emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
last_bytes -= 2;
if (last_bytes)
{
--- 4563,4569 ----
RTX_UNCHANGING_P (mem) = dst_unchanging_p;
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
! emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
last_bytes -= 2;
if (last_bytes)
{
*************** arm_gen_movstrqi (operands)
*** 4581,4587 ****
RTX_UNCHANGING_P (mem) = dst_unchanging_p;
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
! emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
}
}
--- 4581,4587 ----
RTX_UNCHANGING_P (mem) = dst_unchanging_p;
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
! emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
}
}
*************** arm_reload_out_hi (operands)
*** 5119,5141 ****
{
emit_insn (gen_movqi (gen_rtx_MEM (QImode,
plus_constant (base, offset + 1)),
! gen_rtx_SUBREG (QImode, outval, 0)));
emit_insn (gen_lshrsi3 (scratch,
gen_rtx_SUBREG (SImode, outval, 0),
GEN_INT (8)));
emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
! gen_rtx_SUBREG (QImode, scratch, 0)));
}
else
{
emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
! gen_rtx_SUBREG (QImode, outval, 0)));
emit_insn (gen_lshrsi3 (scratch,
gen_rtx_SUBREG (SImode, outval, 0),
GEN_INT (8)));
emit_insn (gen_movqi (gen_rtx_MEM (QImode,
plus_constant (base, offset + 1)),
! gen_rtx_SUBREG (QImode, scratch, 0)));
}
}
--- 5119,5141 ----
{
emit_insn (gen_movqi (gen_rtx_MEM (QImode,
plus_constant (base, offset + 1)),
! gen_lowpart (QImode, outval)));
emit_insn (gen_lshrsi3 (scratch,
gen_rtx_SUBREG (SImode, outval, 0),
GEN_INT (8)));
emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
! gen_lowpart (QImode, scratch)));
}
else
{
emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
! gen_lowpart (QImode, outval)));
emit_insn (gen_lshrsi3 (scratch,
gen_rtx_SUBREG (SImode, outval, 0),
GEN_INT (8)));
emit_insn (gen_movqi (gen_rtx_MEM (QImode,
plus_constant (base, offset + 1)),
! gen_lowpart (QImode, scratch)));
}
}
Index: gcc/config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.92
diff -c -3 -p -w -r1.92 arm.md
*** arm.md 2002/03/15 17:06:58 1.92
--- arm.md 2002/03/18 10:03:33
***************
*** 3386,3392 ****
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
! "TARGET_ARM && (GET_CODE (operands[1]) != MEM)"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
""
--- 3386,3392 ----
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
! "TARGET_ARM && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
""
***************
*** 4285,4291 ****
[(set (match_dup 4) (match_dup 3))
(set (match_dup 2)
(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
! (set (match_operand 1 "" "") (subreg:QI (match_dup 2) 0))]
"TARGET_ARM"
"
{
--- 4285,4291 ----
[(set (match_dup 4) (match_dup 3))
(set (match_dup 2)
(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
! (set (match_operand 1 "" "") (subreg:QI (match_dup 2) 3))]
"TARGET_ARM"
"
{
***************
*** 4309,4315 ****
(define_expand "storeinthi"
[(set (match_operand 0 "" "")
(subreg:QI (match_operand 1 "" "") 0))
! (set (match_dup 3) (subreg:QI (match_dup 2) 0))]
"TARGET_ARM"
"
{
--- 4309,4315 ----
(define_expand "storeinthi"
[(set (match_operand 0 "" "")
(subreg:QI (match_operand 1 "" "") 0))
! (set (match_dup 3) (match_dup 2))]
"TARGET_ARM"
"
{
***************
*** 4348,4353 ****
--- 4348,4354 ----
operands[3] = adjust_address (op0, QImode, 1);
operands[0] = adjust_address (operands[0], QImode, 0);
+ operands[2] = gen_lowpart (QImode, operands[2]);
}"
)
***************
*** 4410,4416 ****
}
emit_insn (gen_movsi (reg, GEN_INT (val)));
! operands[1] = gen_rtx_SUBREG (HImode, reg, 0);
}
else if (!arm_arch4)
{
--- 4411,4417 ----
}
emit_insn (gen_movsi (reg, GEN_INT (val)));
! operands[1] = gen_lowpart (HImode, reg);
}
else if (!arm_arch4)
{
***************
*** 4807,4813 ****
rtx reg = gen_reg_rtx (SImode);
emit_insn (gen_movsi (reg, operands[1]));
! operands[1] = gen_rtx_SUBREG (QImode, reg, 0);
}
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (QImode, operands[1]);
--- 4808,4814 ----
rtx reg = gen_reg_rtx (SImode);
emit_insn (gen_movsi (reg, operands[1]));
! operands[1] = gen_lowpart (QImode, reg);
}
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (QImode, operands[1]);
***************
*** 4850,4856 ****
if (GET_CODE (operands[0]) != REG)
abort ();
! operands[0] = gen_rtx (SUBREG, SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
DONE;
}
--- 4851,4857 ----
if (GET_CODE (operands[0]) != REG)
abort ();
! operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
DONE;
}