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Remove some conversions added by my previous change
- From: kenner at vlsi1 dot ultra dot nyu dot edu (Richard Kenner)
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 24 Feb 02 07:45:43 EST
- Subject: Remove some conversions added by my previous change
Though my previous alpha.md change improved 16-bit arithmetic, it made
32-bit unsigned arithmetic worse in some cases. This fixes most of them.
Tested on alphaev56-dec-osf4.0c.
Sun Feb 24 07:41:31 2002 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
* optabs.c (widen_operand): Only call convert_modes for
promoted SUBREG if signedness matches.
* config/alpha/alpha.md (*addsi_se2, *subsi_se2): New patterns.
*** optabs.c 2002/01/12 14:05:32 1.122
--- optabs.c 2002/02/24 10:41:42
*************** widen_operand (op, mode, oldmode, unsign
*** 192,196 ****
if (! no_extend
|| GET_MODE (op) == VOIDmode
! || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op)))
return convert_modes (mode, oldmode, op, unsignedp);
--- 192,197 ----
if (! no_extend
|| GET_MODE (op) == VOIDmode
! || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op)
! && SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp))
return convert_modes (mode, oldmode, op, unsignedp);
*** config/alpha/alpha.md 2002/02/22 21:18:25 1.181
--- config/alpha/alpha.md 2002/02/24 10:41:52
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 565,568 ****
--- 565,579 ----
subl %r1,%n2,%0")
+ (define_insn "*addsi_se2"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (sign_extend:DI
+ (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
+ (match_operand:DI 2 "sext_add_operand" "rI,O"))
+ 0)))]
+ ""
+ "@
+ addl %r1,%2,%0
+ subl %r1,%n2,%0")
+
(define_split
[(set (match_operand:DI 0 "register_operand" "")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 842,845 ****
--- 853,865 ----
(sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
+ ""
+ "subl %r1,%2,%0")
+
+ (define_insn "*subsi_se2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+ (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
+ 0)))]
""
"subl %r1,%2,%0")