This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: powerpc patch 3 of 9
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: David Edelsohn <dje at watson dot ibm dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Thu, 21 Feb 2002 09:32:53 +1030
- Subject: Re: powerpc patch 3 of 9
- References: <20020220110046.GJ1054@bubble.sa.bigpond.net.au>
On Wed, Feb 20, 2002 at 09:30:46PM +1030, Alan Modra wrote:
>
> + /* We have to be careful here. This predicate is used on
> + PowerPC64 with SImode AND expressions to generate an
> + rlwinm. instruction. This rotate insn copies the low 32 bits
> + of the reg to the high 32 bits, rotates (by 0), then masks.
> + The mask is generated from bits MB+32 thru ME+32, and if it
> + wraps (ie. MB > ME) will have 1's in the high order 32 bits.
> + We wouldn't care about the high bits, except that we are
> + using the result to set cr0. Note that if we're not
> + interested in the result of the AND besides setting cr0, then
> + we could rotate such that the mask never needed to wrap, but
> + that would mean further complicating rs6000.md. */
Uh, Oh. This comment appears to be wrong as regards not caring about
the high bits. Peter Bergner just sent me a simple testcase
unsigned long foo (unsigned long base, unsigned int val)
{
return base + (val & 0x80000001);
}
At -O2, the zero extend of the SImode "val & 0x80000001" expression is
removed. This isn't a bug introduced by my patch; It's a problem
with the existing andsi pattern. I'm testing a fix now - basically
rolling const_and_operand into and_operand so that the 'T' constraint
is a little tighter for ppc64.
--
Alan Modra
IBM OzLabs - Linux Technology Centre