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Re: fix aix -fcprop-register miscompilation
On Wed, Jan 09, 2002 at 04:20:02AM -0500, Hans-Peter Nilsson wrote:
> /home/hp/cvs_areas/combined/cvs_write/newlib/libm/math/er_lgamma.c:209:
> insn does not satisfy its constraints:
> (insn 602 601 184 (set (reg/v:SI 10 r10 [29])
> (and:SI (reg:SI 12 r12 [29])
> (reg/v:SI 10 r10 [29]))) 28 {andsi3}
A latent bug in the backend. Matching constraints must match,
even if the operand is marked commutative. This because when
we looked for commutativity during reload, we swapped the
operands around.
Here we had
(set (reg r10) (and (reg r12) (const_int 1)))
which is perfectly valid, then split this to
(set (reg r10) (const_int 1))
(set (reg r10) (and (reg r12) (reg r10)))
which isn't valid -- the match must come first. I have no idea
why this didn't fail before.
Also a bug fix to get the thing to build at all on 64-bit hosts.
r~
* config/m32r/m32r.c (move_src_operand): Fix 32-bit int test.
* config/m32r/m32r.md (and ior xor splitters): Swap operands
to match insn patterns.
Index: m32r.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m32r/m32r.c,v
retrieving revision 1.40
diff -c -p -d -u -r1.40 m32r.c
--- m32r.c 2002/01/03 17:40:03 1.40
+++ m32r.c 2002/01/09 10:54:09
@@ -793,7 +793,13 @@ move_src_operand (op, mode)
loadable with one insn, and split the rest into two. The instances
where this would help should be rare and the current way is
simpler. */
- return UINT32_P (INTVAL (op));
+ if (HOST_BITS_PER_WIDE_INT > 32)
+ {
+ HOST_WIDE_INT rest = INTVAL (op) >> 31;
+ return (rest == 0 || rest == -1);
+ }
+ else
+ return 1;
case LABEL_REF :
return TARGET_ADDR24;
case CONST_DOUBLE :
Index: m32r.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m32r/m32r.md,v
retrieving revision 1.22
diff -c -p -d -u -r1.22 m32r.md
--- m32r.md 2001/11/19 18:30:01 1.22
+++ m32r.md 2002/01/09 10:54:09
@@ -1032,7 +1032,7 @@
(match_operand:SI 2 "int8_operand" "")))]
"optimize_size && m32r_not_same_reg (operands[0], operands[1])"
[(set (match_dup 0) (match_dup 2))
- (set (match_dup 0) (and:SI (match_dup 1) (match_dup 0)))]
+ (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
"")
(define_insn "iorsi3"
@@ -1064,7 +1064,7 @@
(match_operand:SI 2 "int8_operand" "")))]
"optimize_size && m32r_not_same_reg (operands[0], operands[1])"
[(set (match_dup 0) (match_dup 2))
- (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 0)))]
+ (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
"")
(define_insn "xorsi3"
@@ -1096,7 +1096,7 @@
(match_operand:SI 2 "int8_operand" "")))]
"optimize_size && m32r_not_same_reg (operands[0], operands[1])"
[(set (match_dup 0) (match_dup 2))
- (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 0)))]
+ (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
"")
(define_insn "negsi2"