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Re: PATCH, rs6000 (alpha?) long const take 2
- From: Tom Rix <trix at redhat dot com>
- To: Richard Henderson <rth at redhat dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Tue, 01 Jan 2002 15:16:57 -0600
- Subject: Re: PATCH, rs6000 (alpha?) long const take 2
- References: <3C2DDFAE.83C9257F@redhat.com> <20011229113944.B15556@redhat.com> <3C2E36AF.9617D83C@redhat.com> <20011229161316.A27391@redhat.com> <3C2E84BF.42C63D38@redhat.com> <20011229193035.A29404@redhat.com> <3C2EA94D.801FCA14@redhat.com> <20011229230113.A29623@redhat.com>
Richard Henderson wrote:
> On Sat, Dec 29, 2001 at 11:42:37PM -0600, Tom Rix wrote:
> > (insn 37 35 39 (set (reg:DI 0 r0) <<< this is the problem >>>
> >
> > (plus:DI (reg:DI 0 r0)
> > (const_int -131072 [0xfffffffffffe0000]))) -1 (insn_list 35
> > (nil))
> > (nil))
>
> Actually, the real problem is that addis must be used
> with some register other than r0. So the temp register
> chosen should be other than r0.
Yes.
Here is the original patch modified to do the addsi if the reg is not 0.
Tom
--
Tom Rix
GCC Engineer
trix@redhat.com
2002-01-01 Tom Rix <trix@redhat.com>
* config/rs6000/rs6000.c (rs6000_emit_set_long_const): Fix for use by
rs6000_emit_allocate_stack.
diff -rcp gcc-old/gcc/config/rs6000/rs6000.c gcc/gcc/config/rs6000/rs6000.c
*** gcc-old/gcc/config/rs6000/rs6000.c Tue Jan 1 07:12:35 2002
--- gcc/gcc/config/rs6000/rs6000.c Tue Jan 1 07:34:25 2002
*************** rs6000_emit_set_long_const (dest, c1, c2
*** 2002,2008 ****
}
else
{
! HOST_WIDE_INT d1, d2, d3, d4;
/* Decompose the entire word */
#if HOST_BITS_PER_WIDE_INT >= 64
--- 2002,2013 ----
}
else
{
! HOST_WIDE_INT d1, d2, d2_s, d3, d4;
!
! /* This function is called by rs6000_emit_allocate_stack after reload
! with a dest of r0. r0 is an invalid register for addsi. Use an addi
! and a shift instead. */
! int regnum = REGNO (dest);
/* Decompose the entire word */
#if HOST_BITS_PER_WIDE_INT >= 64
*************** rs6000_emit_set_long_const (dest, c1, c2
*** 2011,2016 ****
--- 2016,2022 ----
d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
c1 -= d1;
d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ d2_s = d2 >> 16;
c1 = (c1 - d2) >> 32;
d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
c1 -= d3;
*************** rs6000_emit_set_long_const (dest, c1, c2
*** 2021,2026 ****
--- 2027,2033 ----
d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
c1 -= d1;
d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ d2_s = d2 >> 16;
if (c1 != d2)
abort ();
c2 += (d2 < 0);
*************** rs6000_emit_set_long_const (dest, c1, c2
*** 2039,2056 ****
emit_move_insn (dest,
gen_rtx_PLUS (DImode, dest, GEN_INT (d3)));
}
! else
emit_move_insn (dest, GEN_INT (d3));
/* Shift it into place */
if (d3 != 0 || d4 != 0)
! emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
/* Add in the low bits. */
if (d2 != 0)
! emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2)));
if (d1 != 0)
! emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1)));
}
return dest;
--- 2046,2085 ----
emit_move_insn (dest,
gen_rtx_PLUS (DImode, dest, GEN_INT (d3)));
}
! else if (d3 != 0)
emit_move_insn (dest, GEN_INT (d3));
/* Shift it into place */
if (d3 != 0 || d4 != 0)
! if (regnum == 0 && d2 != 0)
! emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
! else
! emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
/* Add in the low bits. */
if (d2 != 0)
! {
! if (d3 != 0 || d4 != 0)
! {
! if (regnum == 0)
! {
! emit_move_insn (dest, gen_rtx_PLUS (DImode, dest,
! GEN_INT (d2_s)));
! emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest,
! GEN_INT (16)));
! }
! else
! emit_move_insn (dest, gen_rtx_PLUS (DImode, dest,
! GEN_INT (d2)));
! }
! else
! emit_move_insn (dest, GEN_INT (d2));
! }
if (d1 != 0)
! if (d2 != 0 || d3 != 0 || d4 != 0)
! emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1)));
! else
! emit_move_insn (dest, GEN_INT (d1));
}
return dest;